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Searched refs:CLK_MM_DISP_RDMA0 (Results 1 – 24 of 24) sorted by relevance

/linux-6.3-rc2/drivers/clk/mediatek/
A Dclk-mt6765-mm.c42 GATE_MM(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_ck", 10),
A Dclk-mt8183-mm.c59 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 23),
A Dclk-mt8167-mm.c63 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "smi_mm", 11),
A Dclk-mt8186-mm.c36 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "top_disp", 3),
A Dclk-mt6779-mm.c59 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 23),
A Dclk-mt6797-mm.c64 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 19),
A Dclk-mt8192-mm.c46 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "disp_sel", 3),
A Dclk-mt6795-mm.c51 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
A Dclk-mt8173-mm.c65 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
A Dclk-mt2712-mm.c80 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
/linux-6.3-rc2/include/dt-bindings/clock/
A Dmt8167-clk.h90 #define CLK_MM_DISP_RDMA0 11 macro
A Dmediatek,mt6795-clk.h237 #define CLK_MM_DISP_RDMA0 18 macro
A Dmt6797-clk.h234 #define CLK_MM_DISP_RDMA0 20 macro
A Dmt6765-clk.h261 #define CLK_MM_DISP_RDMA0 10 macro
A Dmt8173-clk.h265 #define CLK_MM_DISP_RDMA0 18 macro
A Dmt2712-clk.h319 #define CLK_MM_DISP_RDMA0 18 macro
A Dmt6779-clk.h363 #define CLK_MM_DISP_RDMA0 23 macro
A Dmt8183-clk.h331 #define CLK_MM_DISP_RDMA0 22 macro
A Dmt8186-clk.h304 #define CLK_MM_DISP_RDMA0 3 macro
A Dmt8192-clk.h427 #define CLK_MM_DISP_RDMA0 3 macro
/linux-6.3-rc2/Documentation/devicetree/bindings/display/mediatek/
A Dmediatek,rdma.yaml115 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
/linux-6.3-rc2/arch/arm64/boot/dts/mediatek/
A Dmt8173.dtsi1090 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
A Dmt8192.dtsi1353 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
A Dmt8183.dtsi1873 clocks = <&mmsys CLK_MM_DISP_RDMA0>;

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