Searched refs:CLK_MM_DISP_SPLIT0 (Results 1 – 8 of 8) sorted by relevance
| /linux-6.3-rc2/Documentation/devicetree/bindings/display/mediatek/ |
| A D | mediatek,split.yaml | 63 clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
|
| /linux-6.3-rc2/drivers/clk/mediatek/ |
| A D | clk-mt6795-mm.c | 61 GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),
|
| A D | clk-mt8173-mm.c | 75 GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),
|
| A D | clk-mt2712-mm.c | 90 GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),
|
| /linux-6.3-rc2/include/dt-bindings/clock/ |
| A D | mediatek,mt6795-clk.h | 247 #define CLK_MM_DISP_SPLIT0 28 macro
|
| A D | mt8173-clk.h | 275 #define CLK_MM_DISP_SPLIT0 28 macro
|
| A D | mt2712-clk.h | 329 #define CLK_MM_DISP_SPLIT0 28 macro
|
| /linux-6.3-rc2/arch/arm64/boot/dts/mediatek/ |
| A D | mt8173.dtsi | 1182 clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
|
Completed in 12 milliseconds