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Searched refs:CLK_MM_MDP_RDMA0 (Results 1 – 18 of 18) sorted by relevance

/linux-6.3-rc2/drivers/clk/mediatek/
A Dclk-mt6765-mm.c32 GATE_MM(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_ck", 0),
A Dclk-mt8183-mm.c48 GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 12),
A Dclk-mt6779-mm.c48 GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 12),
A Dclk-mt6797-mm.c49 GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 4),
A Dclk-mt6795-mm.c36 GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3),
A Dclk-mt8173-mm.c51 GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3),
A Dclk-mt2712-mm.c65 GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3),
/linux-6.3-rc2/include/dt-bindings/clock/
A Dmediatek,mt6795-clk.h222 #define CLK_MM_MDP_RDMA0 3 macro
A Dmt6797-clk.h219 #define CLK_MM_MDP_RDMA0 5 macro
A Dmt6765-clk.h251 #define CLK_MM_MDP_RDMA0 0 macro
A Dmt8173-clk.h251 #define CLK_MM_MDP_RDMA0 4 macro
A Dmt2712-clk.h304 #define CLK_MM_MDP_RDMA0 3 macro
A Dmt6779-clk.h353 #define CLK_MM_MDP_RDMA0 13 macro
A Dmt8183-clk.h321 #define CLK_MM_MDP_RDMA0 12 macro
/linux-6.3-rc2/Documentation/devicetree/bindings/media/
A Dmediatek,mdp3-rdma.yaml90 clocks = <&mmsys CLK_MM_MDP_RDMA0>,
A Dmediatek-mdp.txt36 clocks = <&mmsys CLK_MM_MDP_RDMA0>,
/linux-6.3-rc2/arch/arm64/boot/dts/mediatek/
A Dmt8173.dtsi1004 clocks = <&mmsys CLK_MM_MDP_RDMA0>,
A Dmt8183.dtsi1791 clocks = <&mmsys CLK_MM_MDP_RDMA0>,

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