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Searched refs:CLK_MM_MM_MDP_WROT0 (Results 1 – 2 of 2) sorted by relevance

/linux-6.3-rc2/drivers/clk/mediatek/
A Dclk-mt8365-mm.c41 GATE_MM0(CLK_MM_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 5),
/linux-6.3-rc2/include/dt-bindings/clock/
A Dmediatek,mt8365-clk.h310 #define CLK_MM_MM_MDP_WROT0 5 macro

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