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Searched refs:CLK_SCLK_MPLL (Results 1 – 5 of 5) sorted by relevance

/linux-6.3-rc2/arch/arm/boot/dts/
A Dexynos4210-trats.dts216 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
224 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
232 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
240 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
A Dexynos4210-universal_c210.dts231 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
239 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
247 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
255 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
A Dexynos4210-i9100.dts313 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
322 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
330 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
339 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
/linux-6.3-rc2/include/dt-bindings/clock/
A Dexynos4.h21 #define CLK_SCLK_MPLL 9 macro
/linux-6.3-rc2/drivers/clk/samsung/
A Dclk-exynos4.c463 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1),
540 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1),
1232 CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_SCLK_MPLL,
1353 clk_hw_get_rate(hws[CLK_SCLK_MPLL]), in exynos4_clk_init()

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