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Searched refs:CLK_SCLK_UART0 (Results 1 – 24 of 24) sorted by relevance

/linux-6.3-rc2/include/dt-bindings/clock/
A Dexynos5410.h22 #define CLK_SCLK_UART0 128 macro
A Dexynos5250.h43 #define CLK_SCLK_UART0 146 macro
A Dexynos7-clk.h37 #define CLK_SCLK_UART0 3 macro
A Dexynos4.h64 #define CLK_SCLK_UART0 151 macro
A Dexynos5420.h29 #define CLK_SCLK_UART0 128 macro
A Dexynos3250.h255 #define CLK_SCLK_UART0 247 macro
A Dexynos5433.h437 #define CLK_SCLK_UART0 36 macro
/linux-6.3-rc2/drivers/clk/samsung/
A Dclk-exynos5410.c212 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
A Dclk-exynos5250.c491 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
A Dclk-exynos3250.c567 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
A Dclk-exynos7.c365 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0",
A Dclk-exynos4.c777 GATE(CLK_SCLK_UART0, "uclk0", "div_uart0", SRC_MASK_PERIL0, 0,
A Dclk-exynos5420.c979 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
A Dclk-exynos5433.c1723 GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
/linux-6.3-rc2/arch/arm/boot/dts/
A Dexynos3250-artik5.dtsi404 assigned-clocks = <&cmu CLK_SCLK_UART0>;
A Dexynos5410.dtsi340 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
A Dexynos3250-monk.dts456 assigned-clocks = <&cmu CLK_SCLK_UART0>;
A Dexynos3250-rinato.dts666 assigned-clocks = <&cmu CLK_SCLK_UART0>;
A Dexynos3250.dtsi687 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
A Dexynos4.dtsi453 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
A Dexynos5250.dtsi1193 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
A Dexynos5420.dtsi1315 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
/linux-6.3-rc2/arch/arm64/boot/dts/exynos/
A Dexynos7.dtsi211 <&clock_top0 CLK_SCLK_UART0>;
A Dexynos5433.dtsi1423 <&cmu_peric CLK_SCLK_UART0>;

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