Searched refs:CLK_SCLK_UART2 (Results 1 – 21 of 21) sorted by relevance
| /linux-6.3-rc2/include/dt-bindings/clock/ |
| A D | exynos5410.h | 24 #define CLK_SCLK_UART2 130 macro
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| A D | exynos5250.h | 45 #define CLK_SCLK_UART2 148 macro
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| A D | exynos7-clk.h | 39 #define CLK_SCLK_UART2 5 macro
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| A D | exynos4.h | 66 #define CLK_SCLK_UART2 153 macro
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| A D | exynos5420.h | 31 #define CLK_SCLK_UART2 130 macro
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| A D | exynos3250.h | 256 #define CLK_SCLK_UART2 248 macro
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| A D | exynos5433.h | 435 #define CLK_SCLK_UART2 34 macro
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| /linux-6.3-rc2/drivers/clk/samsung/ |
| A D | clk-exynos5410.c | 216 GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
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| A D | clk-exynos5250.c | 495 GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
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| A D | clk-exynos3250.c | 563 GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
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| A D | clk-exynos7.c | 361 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2",
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| A D | clk-exynos4.c | 781 GATE(CLK_SCLK_UART2, "uclk2", "div_uart2", SRC_MASK_PERIL0, 8,
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| A D | clk-exynos5420.c | 983 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2",
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| A D | clk-exynos5433.c | 1717 GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
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| /linux-6.3-rc2/arch/arm/boot/dts/ |
| A D | exynos5410.dtsi | 354 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
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| A D | exynos3250.dtsi | 709 clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
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| A D | exynos4.dtsi | 475 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
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| A D | exynos5250.dtsi | 1207 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
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| A D | exynos5420.dtsi | 1329 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
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| /linux-6.3-rc2/arch/arm64/boot/dts/exynos/ |
| A D | exynos7.dtsi | 223 <&clock_top0 CLK_SCLK_UART2>,
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| A D | exynos5433.dtsi | 1447 <&cmu_peric CLK_SCLK_UART2>;
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Completed in 47 milliseconds