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Searched refs:CLK_TOP_AES_FDE_SEL (Results 1 – 4 of 4) sorted by relevance

/linux-6.3-rc2/include/dt-bindings/clock/
A Dmt6765-clk.h158 #define CLK_TOP_AES_FDE_SEL 123 macro
A Dmediatek,mt8365-clk.h101 #define CLK_TOP_AES_FDE_SEL 91 macro
/linux-6.3-rc2/drivers/clk/mediatek/
A Dclk-mt6765.c455 MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_FDE_SEL, "aes_fde_sel",
A Dclk-mt8365.c503 MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_FDE_SEL, "aes_fde_sel",

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