Searched refs:CLK_TOP_APLL1_DIV1 (Results 1 – 4 of 4) sorted by relevance
| /linux-6.3-rc2/include/dt-bindings/clock/ |
| A D | mediatek,mt6795-clk.h | 127 #define CLK_TOP_APLL1_DIV1 116 macro
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| A D | mt8173-clk.h | 132 #define CLK_TOP_APLL1_DIV1 122 macro
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| /linux-6.3-rc2/drivers/clk/mediatek/ |
| A D | clk-mt6795-topckgen.c | 512 DIV_GATE(CLK_TOP_APLL1_DIV1, "apll1_div1", "aud_1_sel", 0x12c, 9, 0x124, 8, 0),
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| A D | clk-mt8173-topckgen.c | 607 DIV_GATE(CLK_TOP_APLL1_DIV1, "apll1_div1", "aud_1_sel", 0x12c, 9, 0x124, 8, 0),
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