Searched refs:CLK_TOP_APLL_DIV0 (Results 1 – 2 of 2) sorted by relevance

/linux-6.3-rc2/include/dt-bindings/clock/
A D	mt2712-clk.h	201 #define CLK_TOP_APLL_DIV0 170 macro
/linux-6.3-rc2/drivers/clk/mediatek/
A D	clk-mt2712.c	939 DIV_ADJ(CLK_TOP_APLL_DIV0, "apll_div0", "i2so1_sel", 0x124, 0, 8),

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