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Searched refs:CLK_TOP_APLL_DIV_PDN7 (Results 1 – 2 of 2) sorted by relevance

/linux-6.3-rc2/include/dt-bindings/clock/
A Dmt2712-clk.h216 #define CLK_TOP_APLL_DIV_PDN7 185 macro
/linux-6.3-rc2/drivers/clk/mediatek/
A Dclk-mt2712.c988 GATE_TOP0(CLK_TOP_APLL_DIV_PDN7, "apll_div_pdn7", "i2si3_sel", 7),

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