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Searched refs:CLK_TOP_AUD_ENGEN1_SEL (Results 1 – 10 of 10) sorted by relevance

/linux-6.3-rc2/include/dt-bindings/clock/
A Dmt8516-clk.h178 #define CLK_TOP_AUD_ENGEN1_SEL 146 macro
A Dmt6765-clk.h149 #define CLK_TOP_AUD_ENGEN1_SEL 114 macro
A Dmediatek,mt8365-clk.h90 #define CLK_TOP_AUD_ENGEN1_SEL 80 macro
A Dmt8192-clk.h55 #define CLK_TOP_AUD_ENGEN1_SEL 43 macro
/linux-6.3-rc2/drivers/clk/mediatek/
A Dclk-mt8516.c398 MUX(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", aud_engen1_parents,
A Dclk-mt8167.c588 MUX(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", aud_engen1_parents,
A Dclk-mt6765.c426 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel",
A Dclk-mt8192.c651 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel",
A Dclk-mt8365.c469 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel",
/linux-6.3-rc2/arch/arm64/boot/dts/mediatek/
A Dmt8192.dtsi878 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,

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