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Searched refs:CLK_TOP_AUD_ENGEN2_SEL (Results 1 – 8 of 8) sorted by relevance

/linux-6.3-rc2/include/dt-bindings/clock/
A Dmt8516-clk.h179 #define CLK_TOP_AUD_ENGEN2_SEL 147 macro
A Dmediatek,mt8365-clk.h91 #define CLK_TOP_AUD_ENGEN2_SEL 81 macro
A Dmt8192-clk.h56 #define CLK_TOP_AUD_ENGEN2_SEL 44 macro
/linux-6.3-rc2/drivers/clk/mediatek/
A Dclk-mt8516.c400 MUX(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", aud_engen2_parents,
A Dclk-mt8167.c590 MUX(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", aud_engen2_parents,
A Dclk-mt8192.c653 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel",
A Dclk-mt8365.c473 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel",
/linux-6.3-rc2/arch/arm64/boot/dts/mediatek/
A Dmt8192.dtsi880 <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,

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