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Searched refs:CLK_TOP_AUD_L_SEL (Results 1 – 4 of 4) sorted by relevance

/linux-6.3-rc2/include/dt-bindings/clock/
A Dmt7986-clk.h78 #define CLK_TOP_AUD_L_SEL 55 macro
A Dmediatek,mt7981-clk.h116 #define CLK_TOP_AUD_L_SEL 103 macro
/linux-6.3-rc2/drivers/clk/mediatek/
A Dclk-mt7986-topckgen.c267 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
A Dclk-mt7981-topckgen.c374 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,

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