Searched refs:CLK_TOP_CAMTG_SEL (Results 1 – 16 of 16) sorted by relevance
| /linux-6.3-rc2/include/dt-bindings/clock/ |
| A D | mt8135-clk.h | 90 #define CLK_TOP_CAMTG_SEL 79 macro
|
| A D | mediatek,mt6795-clk.h | 98 #define CLK_TOP_CAMTG_SEL 87 macro
|
| A D | mt6765-clk.h | 137 #define CLK_TOP_CAMTG_SEL 102 macro
|
| A D | mt8173-clk.h | 100 #define CLK_TOP_CAMTG_SEL 90 macro
|
| A D | mediatek,mt8365-clk.h | 77 #define CLK_TOP_CAMTG_SEL 67 macro
|
| A D | mt2712-clk.h | 137 #define CLK_TOP_CAMTG_SEL 106 macro
|
| A D | mt2701-clk.h | 91 #define CLK_TOP_CAMTG_SEL 80 macro
|
| A D | mt8192-clk.h | 27 #define CLK_TOP_CAMTG_SEL 15 macro
|
| /linux-6.3-rc2/drivers/clk/mediatek/ |
| A D | clk-mt6795-topckgen.c | 465 TOP_MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x60, 0, 3, 7, 0),
|
| A D | clk-mt8173-topckgen.c | 544 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0060, 0, 3, 7),
|
| A D | clk-mt8135.c | 377 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0158, 8, 3, 15),
|
| A D | clk-mt2701.c | 504 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents,
|
| A D | clk-mt2712.c | 755 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel",
|
| A D | clk-mt6765.c | 387 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel",
|
| A D | clk-mt8192.c | 587 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel",
|
| A D | clk-mt8365.c | 432 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents,
|
Completed in 30 milliseconds