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Searched refs:CLK_TOP_CSW_MUX_MFG_SEL (Results 1 – 2 of 2) sorted by relevance

/linux-6.3-rc2/include/dt-bindings/clock/
A Dmt8167-clk.h55 #define CLK_TOP_CSW_MUX_MFG_SEL (CLK_TOP_NR_CLK + 31) macro
/linux-6.3-rc2/drivers/clk/mediatek/
A Dclk-mt8167.c532 MUX(CLK_TOP_CSW_MUX_MFG_SEL, "csw_mux_mfg_sel", csw_mux_mfg_parents,

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