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Searched refs:CLK_TOP_DISP_PWM_SEL (Results 1 – 7 of 7) sorted by relevance

/linux-6.3-rc2/include/dt-bindings/clock/
A Dmt6765-clk.h150 #define CLK_TOP_DISP_PWM_SEL 115 macro
A Dmediatek,mt8365-clk.h93 #define CLK_TOP_DISP_PWM_SEL 83 macro
A Dmt8192-clk.h45 #define CLK_TOP_DISP_PWM_SEL 33 macro
/linux-6.3-rc2/drivers/clk/mediatek/
A Dclk-mt6765.c429 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel",
A Dclk-mt8192.c628 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel",
A Dclk-mt8365.c479 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel",
/linux-6.3-rc2/arch/arm64/boot/dts/mediatek/
A Dmt8192.dtsi693 clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,

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