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Searched refs:CLK_TOP_DI_SEL (Results 1 – 4 of 4) sorted by relevance

/linux-6.3-rc2/include/dt-bindings/clock/
A Dmt2712-clk.h191 #define CLK_TOP_DI_SEL 160 macro
A Dmt2701-clk.h115 #define CLK_TOP_DI_SEL 104 macro
/linux-6.3-rc2/drivers/clk/mediatek/
A Dclk-mt2701.c550 MUX_GATE(CLK_TOP_DI_SEL, "di_sel", di_parents,
A Dclk-mt2712.c876 MUX_GATE(CLK_TOP_DI_SEL, "di_sel",

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