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Searched refs:CLK_TOP_HDCP_SEL (Results 1 – 4 of 4) sorted by relevance

/linux-6.3-rc2/include/dt-bindings/clock/
A Dmt8173-clk.h128 #define CLK_TOP_HDCP_SEL 118 macro
A Dmt2712-clk.h166 #define CLK_TOP_HDCP_SEL 135 macro
/linux-6.3-rc2/drivers/clk/mediatek/
A Dclk-mt8173-topckgen.c600 MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", hdcp_parents, 0x00d0, 8, 2, 15),
A Dclk-mt2712.c820 MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel",

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