1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2020 MediaTek Inc.
4  * Copyright (c) 2020 BayLibre, SAS.
5  * Author: James Liao <jamesjj.liao@mediatek.com>
6  *         Fabien Parent <fparent@baylibre.com>
7  */
8 
9 #ifndef _DT_BINDINGS_CLK_MT8167_H
10 #define _DT_BINDINGS_CLK_MT8167_H
11 
12 /* MT8167 is based on MT8516 */
13 #include <dt-bindings/clock/mt8516-clk.h>
14 
15 /* APMIXEDSYS */
16 
17 #define CLK_APMIXED_TVDPLL		(CLK_APMIXED_NR_CLK + 0)
18 #define CLK_APMIXED_LVDSPLL		(CLK_APMIXED_NR_CLK + 1)
19 #define CLK_APMIXED_HDMI_REF		(CLK_APMIXED_NR_CLK + 2)
20 #define MT8167_CLK_APMIXED_NR_CLK	(CLK_APMIXED_NR_CLK + 3)
21 
22 /* TOPCKGEN */
23 
24 #define CLK_TOP_DSI0_LNTC_DSICK		(CLK_TOP_NR_CLK + 0)
25 #define CLK_TOP_VPLL_DPIX		(CLK_TOP_NR_CLK + 1)
26 #define CLK_TOP_LVDSTX_CLKDIG_CTS	(CLK_TOP_NR_CLK + 2)
27 #define CLK_TOP_HDMTX_CLKDIG_CTS	(CLK_TOP_NR_CLK + 3)
28 #define CLK_TOP_LVDSPLL			(CLK_TOP_NR_CLK + 4)
29 #define CLK_TOP_LVDSPLL_D2		(CLK_TOP_NR_CLK + 5)
30 #define CLK_TOP_LVDSPLL_D4		(CLK_TOP_NR_CLK + 6)
31 #define CLK_TOP_LVDSPLL_D8		(CLK_TOP_NR_CLK + 7)
32 #define CLK_TOP_MIPI_26M		(CLK_TOP_NR_CLK + 8)
33 #define CLK_TOP_TVDPLL			(CLK_TOP_NR_CLK + 9)
34 #define CLK_TOP_TVDPLL_D2		(CLK_TOP_NR_CLK + 10)
35 #define CLK_TOP_TVDPLL_D4		(CLK_TOP_NR_CLK + 11)
36 #define CLK_TOP_TVDPLL_D8		(CLK_TOP_NR_CLK + 12)
37 #define CLK_TOP_TVDPLL_D16		(CLK_TOP_NR_CLK + 13)
38 #define CLK_TOP_PWM_MM			(CLK_TOP_NR_CLK + 14)
39 #define CLK_TOP_CAM_MM			(CLK_TOP_NR_CLK + 15)
40 #define CLK_TOP_MFG_MM			(CLK_TOP_NR_CLK + 16)
41 #define CLK_TOP_SPM_52M			(CLK_TOP_NR_CLK + 17)
42 #define CLK_TOP_MIPI_26M_DBG		(CLK_TOP_NR_CLK + 18)
43 #define CLK_TOP_SCAM_MM			(CLK_TOP_NR_CLK + 19)
44 #define CLK_TOP_SMI_MM			(CLK_TOP_NR_CLK + 20)
45 #define CLK_TOP_26M_HDMI_SIFM		(CLK_TOP_NR_CLK + 21)
46 #define CLK_TOP_26M_CEC			(CLK_TOP_NR_CLK + 22)
47 #define CLK_TOP_32K_CEC			(CLK_TOP_NR_CLK + 23)
48 #define CLK_TOP_GCPU_B			(CLK_TOP_NR_CLK + 24)
49 #define CLK_TOP_RG_VDEC			(CLK_TOP_NR_CLK + 25)
50 #define CLK_TOP_RG_FDPI0		(CLK_TOP_NR_CLK + 26)
51 #define CLK_TOP_RG_FDPI1		(CLK_TOP_NR_CLK + 27)
52 #define CLK_TOP_RG_AXI_MFG		(CLK_TOP_NR_CLK + 28)
53 #define CLK_TOP_RG_SLOW_MFG		(CLK_TOP_NR_CLK + 29)
54 #define CLK_TOP_GFMUX_EMI1X_SEL		(CLK_TOP_NR_CLK + 30)
55 #define CLK_TOP_CSW_MUX_MFG_SEL		(CLK_TOP_NR_CLK + 31)
56 #define CLK_TOP_CAMTG_MM_SEL		(CLK_TOP_NR_CLK + 32)
57 #define CLK_TOP_PWM_MM_SEL		(CLK_TOP_NR_CLK + 33)
58 #define CLK_TOP_SPM_52M_SEL		(CLK_TOP_NR_CLK + 34)
59 #define CLK_TOP_MFG_MM_SEL		(CLK_TOP_NR_CLK + 35)
60 #define CLK_TOP_SMI_MM_SEL		(CLK_TOP_NR_CLK + 36)
61 #define CLK_TOP_SCAM_MM_SEL		(CLK_TOP_NR_CLK + 37)
62 #define CLK_TOP_VDEC_MM_SEL		(CLK_TOP_NR_CLK + 38)
63 #define CLK_TOP_DPI0_MM_SEL		(CLK_TOP_NR_CLK + 39)
64 #define CLK_TOP_DPI1_MM_SEL		(CLK_TOP_NR_CLK + 40)
65 #define CLK_TOP_AXI_MFG_IN_SEL		(CLK_TOP_NR_CLK + 41)
66 #define CLK_TOP_SLOW_MFG_SEL		(CLK_TOP_NR_CLK + 42)
67 #define MT8167_CLK_TOP_NR_CLK		(CLK_TOP_NR_CLK + 43)
68 
69 /* MFGCFG */
70 
71 #define CLK_MFG_BAXI			0
72 #define CLK_MFG_BMEM			1
73 #define CLK_MFG_BG3D			2
74 #define CLK_MFG_B26M			3
75 #define CLK_MFG_NR_CLK			4
76 
77 /* MMSYS */
78 
79 #define CLK_MM_SMI_COMMON		0
80 #define CLK_MM_SMI_LARB0		1
81 #define CLK_MM_CAM_MDP			2
82 #define CLK_MM_MDP_RDMA			3
83 #define CLK_MM_MDP_RSZ0			4
84 #define CLK_MM_MDP_RSZ1			5
85 #define CLK_MM_MDP_TDSHP		6
86 #define CLK_MM_MDP_WDMA			7
87 #define CLK_MM_MDP_WROT			8
88 #define CLK_MM_FAKE_ENG			9
89 #define CLK_MM_DISP_OVL0		10
90 #define CLK_MM_DISP_RDMA0		11
91 #define CLK_MM_DISP_RDMA1		12
92 #define CLK_MM_DISP_WDMA		13
93 #define CLK_MM_DISP_COLOR		14
94 #define CLK_MM_DISP_CCORR		15
95 #define CLK_MM_DISP_AAL			16
96 #define CLK_MM_DISP_GAMMA		17
97 #define CLK_MM_DISP_DITHER		18
98 #define CLK_MM_DISP_UFOE		19
99 #define CLK_MM_DISP_PWM_MM		20
100 #define CLK_MM_DISP_PWM_26M		21
101 #define CLK_MM_DSI_ENGINE		22
102 #define CLK_MM_DSI_DIGITAL		23
103 #define CLK_MM_DPI0_ENGINE		24
104 #define CLK_MM_DPI0_PXL			25
105 #define CLK_MM_LVDS_PXL			26
106 #define CLK_MM_LVDS_CTS			27
107 #define CLK_MM_DPI1_ENGINE		28
108 #define CLK_MM_DPI1_PXL			29
109 #define CLK_MM_HDMI_PXL			30
110 #define CLK_MM_HDMI_SPDIF		31
111 #define CLK_MM_HDMI_ADSP_BCK		32
112 #define CLK_MM_HDMI_PLL			33
113 #define CLK_MM_NR_CLK			34
114 
115 /* IMGSYS */
116 
117 #define CLK_IMG_LARB1_SMI		0
118 #define CLK_IMG_CAM_SMI			1
119 #define CLK_IMG_CAM_CAM			2
120 #define CLK_IMG_SEN_TG			3
121 #define CLK_IMG_SEN_CAM			4
122 #define CLK_IMG_VENC			5
123 #define CLK_IMG_NR_CLK			6
124 
125 /* VDECSYS */
126 
127 #define CLK_VDEC_CKEN			0
128 #define CLK_VDEC_LARB1_CKEN		1
129 #define CLK_VDEC_NR_CLK			2
130 
131 #endif /* _DT_BINDINGS_CLK_MT8167_H */
132