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Searched refs:CLK_TOP_MM_SEL (Results 1 – 18 of 18) sorted by relevance

/linux-6.3-rc2/Documentation/devicetree/bindings/power/
A Dmediatek,power-controller.yaml152 clocks = <&topckgen CLK_TOP_MM_SEL>;
158 clocks = <&topckgen CLK_TOP_MM_SEL>,
165 clocks = <&topckgen CLK_TOP_MM_SEL>;
171 clocks = <&topckgen CLK_TOP_MM_SEL>;
178 clocks = <&topckgen CLK_TOP_MM_SEL>,
/linux-6.3-rc2/include/dt-bindings/clock/
A Dmediatek,mt6795-clk.h93 #define CLK_TOP_MM_SEL 82 macro
A Dmt6765-clk.h133 #define CLK_TOP_MM_SEL 98 macro
A Dmt8173-clk.h95 #define CLK_TOP_MM_SEL 85 macro
A Dmediatek,mt8365-clk.h73 #define CLK_TOP_MM_SEL 63 macro
A Dmt2712-clk.h132 #define CLK_TOP_MM_SEL 101 macro
A Dmt2701-clk.h87 #define CLK_TOP_MM_SEL 76 macro
/linux-6.3-rc2/arch/arm64/boot/dts/mediatek/
A Dmt8173.dtsi459 clocks = <&topckgen CLK_TOP_MM_SEL>;
465 clocks = <&topckgen CLK_TOP_MM_SEL>,
472 clocks = <&topckgen CLK_TOP_MM_SEL>;
478 clocks = <&topckgen CLK_TOP_MM_SEL>;
485 clocks = <&topckgen CLK_TOP_MM_SEL>,
991 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
A Dmt2712e.dtsi284 clocks = <&topckgen CLK_TOP_MM_SEL>,
/linux-6.3-rc2/Documentation/devicetree/bindings/soc/mediatek/
A Dscpsys.txt67 <&topckgen CLK_TOP_MM_SEL>;
/linux-6.3-rc2/drivers/clk/mediatek/
A Dclk-mt6795-topckgen.c458 TOP_MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x40, 24, 3, 31, 0),
A Dclk-mt8173-topckgen.c537 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x0040, 24, 4, 31),
A Dclk-mt2701.c495 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents,
A Dclk-mt2712.c743 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel",
A Dclk-mt6765.c374 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, CLK_CFG_0,
A Dclk-mt8365.c423 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x040, 0x044,
/linux-6.3-rc2/arch/arm/boot/dts/
A Dmt2701.dtsi156 clocks = <&topckgen CLK_TOP_MM_SEL>,
A Dmt7623.dtsi277 clocks = <&topckgen CLK_TOP_MM_SEL>,

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