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Searched refs:CLK_TOP_MSDC30_3_SEL (Results 1 – 10 of 10) sorted by relevance

/linux-6.3-rc2/include/dt-bindings/clock/
A Dmt8135-clk.h83 #define CLK_TOP_MSDC30_3_SEL 72 macro
A Dmediatek,mt6795-clk.h107 #define CLK_TOP_MSDC30_3_SEL 96 macro
A Dmt8173-clk.h109 #define CLK_TOP_MSDC30_3_SEL 99 macro
A Dmt2712-clk.h146 #define CLK_TOP_MSDC30_3_SEL 115 macro
A Dmt2701-clk.h126 #define CLK_TOP_MSDC30_3_SEL 115 macro
/linux-6.3-rc2/drivers/clk/mediatek/
A Dclk-mt6795-topckgen.c477 TOP_MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents, 0x80, 8, 3, 15, 0),
A Dclk-mt8173-topckgen.c559 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents,
A Dclk-mt8135.c367 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents, 0x0148, 16, 3, 23),
A Dclk-mt2701.c575 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents,
A Dclk-mt2712.c775 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel",

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