Searched refs:CLK_TOP_MSDC50_0_HCLK_SEL (Results 1 – 4 of 4) sorted by relevance

/linux-6.3-rc2/include/dt-bindings/clock/
A D	mt6765-clk.h	143 #define CLK_TOP_MSDC50_0_HCLK_SEL 108 macro
A D	mt2712-clk.h	142 #define CLK_TOP_MSDC50_0_HCLK_SEL 111 macro
/linux-6.3-rc2/drivers/clk/mediatek/
A D	clk-mt2712.c	766 MUX_GATE(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc50_0_h_sel",
A D	clk-mt6765.c	407 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc5hclk",

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