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Searched refs:CLK_TOP_MUX_MFG (Results 1 – 6 of 6) sorted by relevance

/linux-6.3-rc2/drivers/clk/mediatek/
A Dclk-mt8183.c477 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MFG, "mfg_sel",
1137 if (top_muxes[i].id == CLK_TOP_MUX_MFG) in clk_mt8183_reg_mfg_mux_notifier()
1178 top_clk_data->hws[CLK_TOP_MUX_MFG]->clk); in clk_mt8183_top_probe()
A Dclk-mt6797.c338 MUX_GATE(CLK_TOP_MUX_MFG, "mfg_sel", mfg_parents, 0x0050, 24, 2, 31),
/linux-6.3-rc2/include/dt-bindings/clock/
A Dmt6797-clk.h20 #define CLK_TOP_MUX_MFG 10 macro
A Dmt8183-clk.h39 #define CLK_TOP_MUX_MFG 3 macro
/linux-6.3-rc2/arch/arm64/boot/dts/mediatek/
A Dmt6797.dtsi213 clocks = <&topckgen CLK_TOP_MUX_MFG>,
A Dmt8183.dtsi875 clocks = <&topckgen CLK_TOP_MUX_MFG>;

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