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Searched refs:CLK_TOP_MUX_MSDC30_2 (Results 1 – 4 of 4) sorted by relevance

/linux-6.3-rc2/include/dt-bindings/clock/
A Dmt6797-clk.h29 #define CLK_TOP_MUX_MSDC30_2 19 macro
A Dmt8183-clk.h46 #define CLK_TOP_MUX_MSDC30_2 10 macro
/linux-6.3-rc2/drivers/clk/mediatek/
A Dclk-mt6797.c352 MUX_GATE(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel", msdc30_2_parents,
A Dclk-mt8183.c512 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel",

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