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Searched refs:CLK_TOP_MUX_MSDC50_0 (Results 1 – 8 of 8) sorted by relevance

/linux-6.3-rc2/include/dt-bindings/clock/
A Dmt6797-clk.h27 #define CLK_TOP_MUX_MSDC50_0 17 macro
A Dmt8183-clk.h44 #define CLK_TOP_MUX_MSDC50_0 8 macro
/linux-6.3-rc2/arch/arm64/boot/dts/mediatek/
A Dmt8183-evb.dts116 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
A Dmt8183-pumpkin.dts154 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
A Dmt8183-kukui.dtsi361 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
A Dmt8183.dtsi1673 clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>,
/linux-6.3-rc2/drivers/clk/mediatek/
A Dclk-mt6797.c348 MUX_GATE(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel", msdc50_0_parents,
A Dclk-mt8183.c506 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel",

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