| /linux-6.3-rc2/include/dt-bindings/clock/ |
| A D | mt7986-clk.h | 54 #define CLK_TOP_PWM_SEL 31 macro
|
| A D | mt7629-clk.h | 87 #define CLK_TOP_PWM_SEL 77 macro
|
| A D | mediatek,mt7981-clk.h | 94 #define CLK_TOP_PWM_SEL 81 macro
|
| A D | mt8516-clk.h | 188 #define CLK_TOP_PWM_SEL 156 macro
|
| A D | mt7622-clk.h | 72 #define CLK_TOP_PWM_SEL 60 macro
|
| A D | mediatek,mt6795-clk.h | 94 #define CLK_TOP_PWM_SEL 83 macro
|
| A D | mt6765-clk.h | 156 #define CLK_TOP_PWM_SEL 121 macro
|
| A D | mt8173-clk.h | 96 #define CLK_TOP_PWM_SEL 86 macro
|
| A D | mediatek,mt8365-clk.h | 99 #define CLK_TOP_PWM_SEL 89 macro
|
| A D | mt2712-clk.h | 133 #define CLK_TOP_PWM_SEL 102 macro
|
| A D | mt2701-clk.h | 94 #define CLK_TOP_PWM_SEL 83 macro
|
| A D | mt8192-clk.h | 66 #define CLK_TOP_PWM_SEL 54 macro
|
| /linux-6.3-rc2/Documentation/devicetree/bindings/pwm/ |
| A D | mediatek,mt2712-pwm.yaml | 83 clocks = <&topckgen CLK_TOP_PWM_SEL>, <&pericfg CLK_PERI_PWM>,
|
| /linux-6.3-rc2/drivers/clk/mediatek/ |
| A D | clk-mt7986-topckgen.c | 188 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010,
|
| A D | clk-mt7981-topckgen.c | 305 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
|
| A D | clk-mt6795-topckgen.c | 460 TOP_MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x50, 0, 2, 7, 0),
|
| A D | clk-mt8173-topckgen.c | 539 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7),
|
| A D | clk-mt7629.c | 497 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
|
| A D | clk-mt8516.c | 420 MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
|
| A D | clk-mt7622.c | 526 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
|
| A D | clk-mt8167.c | 610 MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
|
| A D | clk-mt2701.c | 498 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
|
| A D | clk-mt2712.c | 746 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel",
|
| A D | clk-mt6765.c | 449 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, CLK_CFG_6,
|
| /linux-6.3-rc2/arch/arm/boot/dts/ |
| A D | mt7629.dtsi | 247 clocks = <&topckgen CLK_TOP_PWM_SEL>,
251 assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
|