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Searched refs:CLK_TOP_SYSPLL1_D16 (Results 1 – 16 of 16) sorted by relevance

/linux-6.3-rc2/include/dt-bindings/clock/
A Dmt7629-clk.h38 #define CLK_TOP_SYSPLL1_D16 28 macro
A Dmediatek,mt6795-clk.h55 #define CLK_TOP_SYSPLL1_D16 44 macro
A Dmt6797-clk.h50 #define CLK_TOP_SYSPLL1_D16 40 macro
A Dmt6765-clk.h40 #define CLK_TOP_SYSPLL1_D16 5 macro
A Dmt8173-clk.h57 #define CLK_TOP_SYSPLL1_D16 47 macro
A Dmediatek,mt8365-clk.h20 #define CLK_TOP_SYSPLL1_D16 10 macro
A Dmt2712-clk.h40 #define CLK_TOP_SYSPLL1_D16 9 macro
A Dmt2701-clk.h19 #define CLK_TOP_SYSPLL1_D16 9 macro
/linux-6.3-rc2/drivers/clk/mediatek/
A Dclk-mt6795-topckgen.c409 FACTOR_FLAGS(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "main_h546m", 1, 16, 0),
A Dclk-mt8173-topckgen.c488 FACTOR_FLAGS(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "main_h546m", 1, 16, 0),
A Dclk-mt7629.c407 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "mainpll", 1, 32),
A Dclk-mt6797.c32 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
A Dclk-mt2701.c67 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
A Dclk-mt2712.c65 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1,
A Dclk-mt6765.c88 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
A Dclk-mt8365.c39 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "mainpll", 1, 32),

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