| /linux-6.3-rc2/include/dt-bindings/clock/ |
| A D | mt7629-clk.h | 43 #define CLK_TOP_SYSPLL3_D2 33 macro
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| A D | mt7622-clk.h | 37 #define CLK_TOP_SYSPLL3_D2 25 macro
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| A D | mediatek,mt6795-clk.h | 60 #define CLK_TOP_SYSPLL3_D2 49 macro
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| A D | mt6797-clk.h | 57 #define CLK_TOP_SYSPLL3_D2 47 macro
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| A D | mt6765-clk.h | 46 #define CLK_TOP_SYSPLL3_D2 11 macro
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| A D | mt8173-clk.h | 62 #define CLK_TOP_SYSPLL3_D2 52 macro
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| A D | mediatek,mt8365-clk.h | 26 #define CLK_TOP_SYSPLL3_D2 16 macro
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| A D | mt2712-clk.h | 45 #define CLK_TOP_SYSPLL3_D2 14 macro
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| A D | mt2701-clk.h | 23 #define CLK_TOP_SYSPLL3_D2 13 macro
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| /linux-6.3-rc2/Documentation/devicetree/bindings/spi/ |
| A D | mediatek,spi-mt65xx.yaml | 107 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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| /linux-6.3-rc2/drivers/clk/mediatek/ |
| A D | clk-mt6795-topckgen.c | 414 FACTOR_FLAGS(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "main_h218p4m", 1, 2, 0),
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| A D | clk-mt8173-topckgen.c | 493 FACTOR_FLAGS(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "main_h218p4m", 1, 2, 0),
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| A D | clk-mt7629.c | 412 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10),
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| A D | clk-mt6797.c | 39 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
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| A D | clk-mt7622.c | 404 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10),
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| A D | clk-mt2701.c | 71 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
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| A D | clk-mt2712.c | 75 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1,
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| A D | clk-mt6765.c | 94 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
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| A D | clk-mt8365.c | 45 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10),
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| /linux-6.3-rc2/arch/arm/boot/dts/ |
| A D | mt2701.dtsi | 342 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
402 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
415 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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| A D | mt7623.dtsi | 487 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
566 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
580 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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| A D | mt7629.dtsi | 281 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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| /linux-6.3-rc2/arch/arm64/boot/dts/mediatek/ |
| A D | mt7622.dtsi | 499 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
592 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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| A D | mt8173.dtsi | 761 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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