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Searched refs:CLK_TOP_TVDPLL_D2 (Results 1 – 21 of 21) sorted by relevance

/linux-6.3-rc2/include/dt-bindings/clock/
A Dmt8167-clk.h34 #define CLK_TOP_TVDPLL_D2 (CLK_TOP_NR_CLK + 10) macro
A Dmediatek,mt6795-clk.h66 #define CLK_TOP_TVDPLL_D2 55 macro
A Dmt6797-clk.h97 #define CLK_TOP_TVDPLL_D2 87 macro
A Dmt8173-clk.h68 #define CLK_TOP_TVDPLL_D2 58 macro
A Dmt2712-clk.h104 #define CLK_TOP_TVDPLL_D2 73 macro
A Dmt6779-clk.h92 #define CLK_TOP_TVDPLL_D2 82 macro
A Dmt8183-clk.h117 #define CLK_TOP_TVDPLL_D2 81 macro
A Dmt8186-clk.h125 #define CLK_TOP_TVDPLL_D2 106 macro
A Dmt2701-clk.h58 #define CLK_TOP_TVDPLL_D2 48 macro
A Dmt8192-clk.h132 #define CLK_TOP_TVDPLL_D2 120 macro
/linux-6.3-rc2/drivers/clk/mediatek/
A Dclk-mt6795-topckgen.c421 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_594m", 1, 2),
A Dclk-mt8173-topckgen.c500 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_594m", 1, 2),
A Dclk-mt8186-topckgen.c60 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
A Dclk-mt6797.c79 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
A Dclk-mt8167.c79 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
A Dclk-mt2701.c111 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
A Dclk-mt6779.c80 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
A Dclk-mt2712.c191 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1,
A Dclk-mt8183.c80 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
A Dclk-mt8192.c81 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
/linux-6.3-rc2/arch/arm64/boot/dts/mediatek/
A Dmt8186.dtsi1124 assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>;

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