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Searched refs:CLK_TOP_U2U3_XHCI_SEL (Results 1 – 5 of 5) sorted by relevance

/linux-6.3-rc2/include/dt-bindings/clock/
A Dmt7986-clk.h82 #define CLK_TOP_U2U3_XHCI_SEL 59 macro
A Dmediatek,mt7981-clk.h120 #define CLK_TOP_U2U3_XHCI_SEL 107 macro
/linux-6.3-rc2/drivers/clk/mediatek/
A Dclk-mt7986-topckgen.c278 MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel",
A Dclk-mt7981-topckgen.c385 MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel",
/linux-6.3-rc2/arch/arm64/boot/dts/mediatek/
A Dmt7986a.dtsi337 <&topckgen CLK_TOP_U2U3_XHCI_SEL>;

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