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Searched refs:CLK_VPP0_WARP1_ASYNC_TX (Results 1 – 2 of 2) sorted by relevance

/linux-6.3-rc2/drivers/clk/mediatek/
A Dclk-mt8195-vpp0.c47 GATE_VPP0_0(CLK_VPP0_WARP1_ASYNC_TX, "vpp0_warp1_async_tx", "top_vpp", 11),
/linux-6.3-rc2/include/dt-bindings/clock/
A Dmt8195-clk.h438 #define CLK_VPP0_WARP1_ASYNC_TX 5 macro

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