| /linux-6.3-rc2/Documentation/kbuild/ |
| A D | Kconfig.recursion-issue-01 | 13 # * What values are possible for CORE?
15 # CORE_BELL_A_ADVANCED selects CORE, which means that it influences the values
16 # that are possible for CORE. So for example if CORE_BELL_A_ADVANCED is 'y',
17 # CORE must be 'y' too.
27 # CORE_BELL_A depends on CORE, so CORE influences CORE_BELL_A.
31 # regarding possible values of CORE itself again. Answering the original
32 # question of what are the possible values of CORE would make the kconfig
43 # CORE also consist of a solution to this recursive problem.
47 config CORE config
52 depends on CORE
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| A D | Kconfig.recursion-issue-02 | 25 # have. Let's assume we have some CORE functionality, then the kernel has a
32 # with CORE, one uses "depends on" while the other uses "select". Another
38 # To fix this the "depends on CORE" must be changed to "select CORE", or the
39 # "select CORE" must be changed to "depends on CORE".
49 config CORE config
54 depends on CORE
63 select CORE
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| /linux-6.3-rc2/drivers/net/wireless/mediatek/mt76/mt76x0/ |
| A D | initvals_init.h | 87 { MT_BBP(CORE, 1), 0x00000002 },
88 { MT_BBP(CORE, 4), 0x00000000 },
89 { MT_BBP(CORE, 24), 0x00000000 },
90 { MT_BBP(CORE, 32), 0x4003000a },
91 { MT_BBP(CORE, 42), 0x00000000 },
92 { MT_BBP(CORE, 44), 0x00000000 },
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| A D | phy.c | 191 val = mt76_rr(dev, MT_BBP(CORE, 0)); in mt76x0_phy_wait_bbp_ready()
516 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x0_phy_tssi_dc_calibrate()
521 mt76_wr(dev, MT_BBP(CORE, 34), val); in mt76x0_phy_tssi_dc_calibrate()
534 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x0_phy_tssi_dc_calibrate()
550 mt76_wr(dev, MT_BBP(CORE, 34), val); in mt76x0_phy_tssi_adc_calibrate()
562 mt76_wr(dev, MT_BBP(CORE, 34), 0x80041); in mt76x0_phy_tssi_adc_calibrate()
566 mt76_wr(dev, MT_BBP(CORE, 34), 0x80042); in mt76x0_phy_tssi_adc_calibrate()
570 mt76_wr(dev, MT_BBP(CORE, 34), 0x80043); in mt76x0_phy_tssi_adc_calibrate()
748 data = mt76_rr(dev, MT_BBP(CORE, 1)); in mt76x0_phy_get_delta_power()
998 mt76_set(dev, MT_BBP(CORE, 1), 0x20); in mt76x0_phy_set_channel()
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| /linux-6.3-rc2/drivers/net/wireless/mediatek/mt76/mt76x2/ |
| A D | mac.c | 37 mt76_set(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2_mac_stop()
38 mt76_clear(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2_mac_stop()
40 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2_mac_stop()
41 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2_mac_stop()
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| A D | usb_mac.c | 143 mt76_set(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2u_mac_stop()
144 mt76_clear(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2u_mac_stop()
146 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2u_mac_stop()
147 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2u_mac_stop()
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| A D | pci_phy.c | 83 mt76_rmw_field(dev, MT_BBP(CORE, 32), GENMASK(21, 20), 2); in mt76x2_phy_set_antenna()
85 mt76_rmw_field(dev, MT_BBP(CORE, 33), GENMASK(12, 9), 4); in mt76x2_phy_set_antenna()
94 mt76_rmw_field(dev, MT_BBP(CORE, 32), GENMASK(21, 20), 1); in mt76x2_phy_set_antenna()
96 mt76_rmw_field(dev, MT_BBP(CORE, 33), GENMASK(12, 9), 1); in mt76x2_phy_set_antenna()
107 mt76_clear(dev, MT_BBP(CORE, 32), GENMASK(21, 20)); in mt76x2_phy_set_antenna()
108 mt76_clear(dev, MT_BBP(CORE, 33), GENMASK(12, 9)); in mt76x2_phy_set_antenna()
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| A D | phy.c | 218 if (mt76_rr(dev, MT_BBP(CORE, 34)) & BIT(4)) in mt76x2_phy_tssi_compensate()
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| /linux-6.3-rc2/Documentation/devicetree/bindings/regulator/ |
| A D | nvidia,tegra-regulators-coupling.txt | 11 On Tegra20 SoC's there are 3 coupled regulators: CORE, RTC and CPU.
12 The CORE and RTC voltages shall be in a range of 170mV from each other
18 On Tegra30 SoC's there are 2 coupled regulators: CORE and CPU. The CORE
19 and CPU voltages shall be in a range of 300mV from each other and CORE
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| /linux-6.3-rc2/arch/arm/boot/dts/ |
| A D | uniphier-pro5-epcore.dts | 3 * Device Tree Source for UniPhier Pro5 EP-CORE Board (Pro5-PCIe_EP-CORE)
14 model = "UniPhier Pro5 EP-CORE Board";
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| A D | omap5-core-thermal.dtsi | 3 * Device Tree Source for OMAP543x SoC CORE thermal
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| /linux-6.3-rc2/drivers/infiniband/hw/hfi1/ |
| A D | chip_registers.h | 9 #define CORE 0x000000000000 macro
10 #define CCE (CORE + 0x000000000000)
11 #define ASIC (CORE + 0x000000400000)
12 #define MISC (CORE + 0x000000500000)
13 #define DC_TOP_CSRS (CORE + 0x000000600000)
14 #define CHIP_DEBUG (CORE + 0x000000700000)
15 #define RXE (CORE + 0x000001000000)
16 #define TXE (CORE + 0x000001800000)
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| /linux-6.3-rc2/drivers/cpufreq/ |
| A D | imx-cpufreq-dt.c | 39 CORE, enumerator
73 clk_set_parent(imx7ulp_clks[ARM].clk, imx7ulp_clks[CORE].clk); in imx7ulp_target_intermediate()
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| /linux-6.3-rc2/drivers/gpu/drm/nouveau/dispnv50/ |
| A D | crcc57d.c | 18 u32 crc_args = NVDEF(NVC57D, HEAD_SET_CRC_CONTROL, CONTROLLING_CHANNEL, CORE) | in crcc57d_set_src()
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| A D | crc907d.c | 31 u32 crc_args = NVDEF(NV907D, HEAD_SET_CRC_CONTROL, CONTROLLING_CHANNEL, CORE) | in crc907d_set_src()
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| A D | base907c.c | 166 NVDEF(NV907C, SET_CSC_RED2RED, OWNER, CORE)); in base907c_csc_clr()
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| /linux-6.3-rc2/Documentation/devicetree/bindings/mmc/ |
| A D | litex,mmc.yaml | 29 - description: CORE registers
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| /linux-6.3-rc2/Documentation/devicetree/bindings/mfd/ |
| A D | da9052-i2c.txt | 19 buck1 : regulator BUCK CORE
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| /linux-6.3-rc2/drivers/regulator/ |
| A D | tps68470-regulator.c | 103 TPS68470_REGULATOR(CORE, TPS68470_CORE, tps68470_regulator_ops, 43,
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| /linux-6.3-rc2/arch/arm/mach-omap2/ |
| A D | Kconfig | 263 access SDRAM during CORE DVFS, select Y here. This should boost
264 SDRAM performance at lower CORE OPPs. There are relatively few
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| A D | sleep34xx.S | 354 cmp r4, #0x0 @ Check if previous power state of CORE is OFF
374 cmp r2, #0x0 @ Check if previous power state of CORE is OFF
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| /linux-6.3-rc2/drivers/net/wireless/mediatek/mt76/ |
| A D | mt76x02_phy.c | 143 mt76_rmw_field(dev, MT_BBP(CORE, 1), MT_BBP_CORE_R1_BW, core_val); in mt76x02_phy_set_bw()
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| /linux-6.3-rc2/Documentation/devicetree/bindings/remoteproc/ |
| A D | qcom,sdm845-adsp-pil.yaml | 50 - description: Q6SP6SS CORE clock
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| /linux-6.3-rc2/Documentation/gpu/ |
| A D | komeda-kms.rst | 328 achieve this, split the komeda device into two layers: CORE and CHIP.
330 - CORE: for common features and capabilities handling.
333 CORE can access CHIP by three chip function structures:
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| /linux-6.3-rc2/Documentation/arm/omap/ |
| A D | omap_pm.rst | 42 3. Set the maximum system DMA transfer start latency (CORE pwrdm)::
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