| /linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/ |
| A D | mes_v10_1.c | 687 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, in mes_v10_1_mqd_init()
689 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, in mes_v10_1_mqd_init()
692 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); in mes_v10_1_mqd_init()
694 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); in mes_v10_1_mqd_init()
695 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); in mes_v10_1_mqd_init()
696 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in mes_v10_1_mqd_init()
697 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); in mes_v10_1_mqd_init()
698 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); in mes_v10_1_mqd_init()
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| A D | mes_v11_0.c | 754 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, in mes_v11_0_mqd_init()
756 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, in mes_v11_0_mqd_init()
758 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); in mes_v11_0_mqd_init()
759 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); in mes_v11_0_mqd_init()
760 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in mes_v11_0_mqd_init()
761 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); in mes_v11_0_mqd_init()
762 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); in mes_v11_0_mqd_init()
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| A D | amdgpu_amdkfd_gfx_v11.c | 224 CP_HQD_PQ_CONTROL, QUEUE_SIZE); in hqd_load_v11()
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| A D | amdgpu_amdkfd_gfx_v10.c | 252 CP_HQD_PQ_CONTROL, QUEUE_SIZE); in kgd_hqd_load()
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| A D | amdgpu_amdkfd_gfx_v9.c | 266 CP_HQD_PQ_CONTROL, QUEUE_SIZE); in kgd_gfx_v9_hqd_load()
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| A D | amdgpu_amdkfd_gfx_v10_3.c | 239 CP_HQD_PQ_CONTROL, QUEUE_SIZE); in hqd_load_v10_3()
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| A D | gfx_v8_0.c | 4463 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, in gfx_v8_0_mqd_init()
4465 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, in gfx_v8_0_mqd_init()
4468 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); in gfx_v8_0_mqd_init()
4470 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); in gfx_v8_0_mqd_init()
4471 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); in gfx_v8_0_mqd_init()
4472 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in gfx_v8_0_mqd_init()
4473 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); in gfx_v8_0_mqd_init()
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| A D | gfx_v9_0.c | 3299 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, in gfx_v9_0_mqd_init()
3301 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, in gfx_v9_0_mqd_init()
3304 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); in gfx_v9_0_mqd_init()
3306 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); in gfx_v9_0_mqd_init()
3307 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); in gfx_v9_0_mqd_init()
3308 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in gfx_v9_0_mqd_init()
3309 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); in gfx_v9_0_mqd_init()
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| A D | gfx_v11_0.c | 3855 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, in gfx_v11_0_compute_mqd_init()
3857 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, in gfx_v11_0_compute_mqd_init()
3859 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); in gfx_v11_0_compute_mqd_init()
3860 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); in gfx_v11_0_compute_mqd_init()
3861 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in gfx_v11_0_compute_mqd_init()
3862 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); in gfx_v11_0_compute_mqd_init()
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| A D | gfx_v10_0.c | 6652 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, in gfx_v10_0_compute_mqd_init()
6654 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, in gfx_v10_0_compute_mqd_init()
6657 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); in gfx_v10_0_compute_mqd_init()
6659 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); in gfx_v10_0_compute_mqd_init()
6660 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); in gfx_v10_0_compute_mqd_init()
6661 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in gfx_v10_0_compute_mqd_init()
6662 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); in gfx_v10_0_compute_mqd_init()
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| /linux-6.3-rc2/drivers/gpu/drm/radeon/ |
| A D | cikd.h | 1519 #define CP_HQD_PQ_CONTROL 0xC958 macro
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| A D | cik.c | 4658 mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL); in cik_cp_compute_resume()
4673 WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control); in cik_cp_compute_resume()
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