| /linux-6.3-rc2/Documentation/devicetree/bindings/spi/ |
| A D | spi-mux.yaml | 23 | +--+++-+ | CS-X +------+\ +--+--+ +--+--+ +--+--+ +--+--+
24 | | SPI +-|-------+ Mux |\\ CS-0 | | | |
25 | +------+ | +--+---+\\\-------/ CS-1 | | |
26 | | | \\\----------------/ CS-2 | |
27 | +------+ | | \\-------------------------/ CS-3 |
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| A D | spi-davinci.txt | 40 For example to have 3 internal CS and 2 GPIO CS, user could define
42 where first three are internal CS and last two are GPIO CS.
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| A D | spi-controller.yaml | 34 So if, for example, the controller has 4 CS lines, and the
51 Each table entry defines how the CS pin is to be physically
54 device node | cs-gpio | CS pin state active | Note
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| A D | spi-peripheral-props.yaml | 49 Delay in nanoseconds to be introduced by the controller after CS is
54 Delay in nanoseconds to be introduced by the controller before CS is
59 Delay in nanoseconds to be introduced by the controller after CS is
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| /linux-6.3-rc2/arch/x86/um/os-Linux/ |
| A D | mcontext.c | 18 COPY(EIP); COPY_SEG_CPL3(CS); COPY(EFL); COPY_SEG_CPL3(SS); in get_regs_from_mc()
28 COPY2(CS, CSGSFS); in get_regs_from_mc()
29 regs->gp[CS / sizeof(unsigned long)] &= 0xffff; in get_regs_from_mc()
30 regs->gp[CS / sizeof(unsigned long)] |= 3; in get_regs_from_mc()
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| /linux-6.3-rc2/tools/perf/arch/x86/tests/ |
| A D | regs_load.S | 14 #define CS 10 * 8 macro
47 movq $0, CS(%rdi)
84 movl $0, CS(%edi)
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| /linux-6.3-rc2/Documentation/devicetree/bindings/memory-controllers/ |
| A D | st,stm32-fmc2-ebi.yaml | 76 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
77 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
78 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
79 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
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| A D | atmel,ebi.txt | 25 The first cell encodes the CS.
26 The second cell encode the offset into the CS memory
31 - ranges: Encodes CS to memory region association.
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| /linux-6.3-rc2/arch/x86/include/uapi/asm/ |
| A D | ptrace-abi.h | 20 #define CS 13 macro
56 #define CS 136 macro
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| /linux-6.3-rc2/arch/x86/entry/ |
| A D | entry_64.S | 161 cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */
409 testb $3, CS-ORIG_RAX(%rsp)
475 testb $3, CS-ORIG_RAX(%rsp)
530 testb $3, CS-ORIG_RAX(%rsp)
629 testb $3, CS(%rsp)
675 testb $3, CS(%rsp)
1061 testb $3, CS+8(%rsp)
1142 testb $3, CS(%rsp)
1203 testb $3, CS-RIP+8(%rsp)
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| /linux-6.3-rc2/Documentation/devicetree/bindings/display/samsung/ |
| A D | samsung,exynos7-decon.yaml | 52 Clock cycles for the active period of CS is enabled.
58 Clock cycles for the active period of CS is disabled until write
65 Clock cycles for the active period of CS signal is enabled until
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| A D | samsung,fimd.yaml | 70 Clock cycles for the active period of CS is enabled.
76 Clock cycles for the active period of CS is disabled until write
83 Clock cycles for the active period of CS signal is enabled until
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| /linux-6.3-rc2/Documentation/devicetree/bindings/mtd/ |
| A D | arm,pl353-nand-r2p1.yaml | 24 - description: CS with regard to the parent ranges property
41 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
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| A D | nand-controller.yaml | 140 cs-gpios = <0>, <&gpioA 1>; /* A single native CS is available */
145 reg = <0>; /* Native CS */
150 reg = <1>; /* GPIO CS */
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| A D | atmel-nand.txt | 33 - reg: describes the CS lines assigned to the NAND device. If the NAND device
34 exposes multiple CS lines (multi-dies chips), your reg property will
36 1st entry: the CS line this NAND chip is connected to
43 - cs-gpios: the GPIO(s) used to control the CS line.
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| /linux-6.3-rc2/arch/x86/um/ |
| A D | ptrace_64.c | 42 [CS >> 3] = HOST_CS,
86 case CS: in putreg()
162 case CS: in getreg()
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| A D | user-offsets.c | 33 DEFINE(HOST_CS, CS); in foo()
62 DEFINE_LONGS(HOST_CS, CS); in foo()
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| A D | ptrace_32.c | 69 [CS] = HOST_CS,
109 case CS: in putreg()
155 case CS: in getreg()
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| /linux-6.3-rc2/Documentation/devicetree/bindings/bus/ |
| A D | imx-weim.txt | 21 - #size-cells: Must be set to 1 to allow CS address passing
31 Purpose Register controller that contains WEIM CS GPR
34 values depending on the CS space configuration.
59 child node. We get the CS indexes from the address
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| A D | qcom,ebi2.txt | 79 the data bus. They are inserted when reading one CS and switching to another
80 CS or read followed by write on the same CS. Valid values 0 thru 15. Minimum
84 WE is asserted until CS is asserted. With a hold of 1 (value = 0), the CS
103 read transfer. For a single read transfer this will be the time from CS
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| /linux-6.3-rc2/Documentation/devicetree/bindings/memory-controllers/ddr/ |
| A D | jedec,lpddr-channel.yaml | 10 An LPDDR channel is a completely independent set of LPDDR pins (DQ, CA, CS,
32 chips, and the CA, CS, etc. pins of the different chips all shorted
57 state of the CS pins. Different ranks may have different densities and
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| /linux-6.3-rc2/Documentation/devicetree/bindings/iio/proximity/ |
| A D | semtech,sx9324.yaml | 41 Array of 3 entries. Index represent the id of the CS pin.
42 Value indicates how each CS pin is used during phase 0.
131 State of CS pins during sleep mode and idle time.
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| /linux-6.3-rc2/Documentation/input/devices/ |
| A D | iforce-protocol.rst | 40 2B OP LEN DATA CS
43 CS is the checksum. It is equal to the exclusive or of all bytes.
51 The 2B, LEN and CS fields have disappeared, probably because USB handles
234 ff 03 42 03 e8 CS would mean that the device has 1000 bytes of ram available.
245 ff 02 4e 14 CS would stand for 20 effects.
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| /linux-6.3-rc2/Documentation/devicetree/bindings/net/ |
| A D | maxim,ds26522.txt | 5 - reg: SPI CS.
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| /linux-6.3-rc2/Documentation/x86/ |
| A D | entry_64.rst | 68 stack, from the CS of the ptregs area of the kernel stack::
71 testl $3,CS+8(%rsp)
95 which might have triggered right after a normal entry wrote CS to the
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