| /linux-6.3-rc2/drivers/scsi/aacraid/ |
| A D | aacraid.h | 1083 #define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) argument
1084 #define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) argument
1085 #define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR)) argument
1086 #define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR)) argument
1145 #define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR)) argument
1146 #define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR)) argument
1147 #define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR)) argument
1163 #define rkt_readb(AEP, CSR) readb(&((AEP)->regs.rkt->CSR)) argument
1164 #define rkt_readl(AEP, CSR) readl(&((AEP)->regs.rkt->CSR)) argument
1211 #define src_readb(AEP, CSR) readb(&((AEP)->regs.src.bar0->CSR)) argument
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| /linux-6.3-rc2/Documentation/devicetree/bindings/gnss/ |
| A D | sirfstar.yaml | 16 by CSR (Cambridge Silicon Radio) and in 2012 the CSR GPS business was
17 acquired by Samsung, while some products remained with CSR. In 2014 CSR
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| /linux-6.3-rc2/drivers/dma/ |
| A D | txx9dmac.c | 296 channel64_readl(dc, CSR)); in txx9dmac_dump_regs()
308 channel32_readl(dc, CSR)); in txx9dmac_dump_regs()
493 d->SAIR, d->DAIR, d->CCR, d->CSR); in txx9dmac_dump_desc()
519 channel_writel(dc, CSR, errors); in txx9dmac_handle_error()
545 csr = channel64_readl(dc, CSR); in txx9dmac_scan_descriptors()
546 channel64_writel(dc, CSR, csr); in txx9dmac_scan_descriptors()
549 csr = channel32_readl(dc, CSR); in txx9dmac_scan_descriptors()
550 channel32_writel(dc, CSR, csr); in txx9dmac_scan_descriptors()
611 csr = channel_readl(dc, CSR); in txx9dmac_chan_tasklet()
629 channel_readl(dc, CSR)); in txx9dmac_chan_interrupt()
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| A D | txx9dmac.h | 78 TXX9_DMA_REG32(CSR); /* Channel Status Register */
88 u32 CSR; member
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| /linux-6.3-rc2/Documentation/devicetree/bindings/clock/ |
| A D | xgene.txt | 36 - reg : shall be a list of address and length pairs describing the CSR
49 - csr-offset : Offset to the CSR reset register from the reset address base.
51 - csr-mask : CSR reset mask bit. Default is 0xF.
54 - enable-mask : CSR enable mask bit. Default is 0xF.
55 - divider-offset : Offset to the divider CSR register from the divider base.
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| /linux-6.3-rc2/drivers/staging/qlge/ |
| A D | qlge_mpi.c | 9 tmp = qlge_read32(qdev, CSR); in qlge_unpause_mpi_risc()
13 qlge_write32(qdev, CSR, CSR_CMD_CLR_PAUSE); in qlge_unpause_mpi_risc()
23 qlge_write32(qdev, CSR, CSR_CMD_SET_PAUSE); in qlge_pause_mpi_risc()
25 tmp = qlge_read32(qdev, CSR); in qlge_pause_mpi_risc()
39 qlge_write32(qdev, CSR, CSR_CMD_SET_RST); in qlge_hard_reset_mpi_risc()
41 tmp = qlge_read32(qdev, CSR); in qlge_hard_reset_mpi_risc()
43 qlge_write32(qdev, CSR, CSR_CMD_CLR_RST); in qlge_hard_reset_mpi_risc()
170 if (qlge_read32(qdev, CSR) & CSR_HRI) in qlge_exec_mb_cmd()
189 qlge_write32(qdev, CSR, CSR_CMD_SET_H2R_INT); in qlge_exec_mb_cmd()
513 qlge_write32(qdev, CSR, CSR_CMD_CLR_R2PCI_INT); in qlge_mpi_handler()
[all …]
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| /linux-6.3-rc2/Documentation/devicetree/bindings/mfd/ |
| A D | fsl,imx8qxp-csr.yaml | 14 Registers(CSR) module represents a set of miscellaneous registers of a
19 should consider all subnodes of the CSR module as separate child devices.
45 description: The possible child devices of the CSR module.
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| /linux-6.3-rc2/Documentation/devicetree/bindings/phy/ |
| A D | fsl,imx8qm-lvds-phy.yaml | 24 by Control and Status Registers(CSR) module in the SoC. The CSR
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| A D | mixel,mipi-dsi-phy.yaml | 50 A phandle which points to Control and Status Registers(CSR) module.
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| /linux-6.3-rc2/Documentation/translations/zh_CN/loongarch/ |
| A D | irq-chip-model.rst | 151 - CPUINTC：即《龙芯架构参考手册卷一》第7.4节所描述的CSR.ECFG/CSR.ESTAT寄存器及其
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| /linux-6.3-rc2/Documentation/devicetree/bindings/display/bridge/ |
| A D | fsl,imx8qxp-pxl2dpi.yaml | 19 The i.MX8qxp PXL2DPI is controlled by Control and Status Registers(CSR) module.
20 The CSR module, as a system controller, contains the PXL2DPI's configuration
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| A D | fsl,imx8qxp-ldb.yaml | 15 The i.MX8qm/qxp LDB is controlled by Control and Status Registers(CSR) module.
16 The CSR module, as a system controller, contains the LDB's configuration
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| /linux-6.3-rc2/drivers/soc/litex/ |
| A D | Kconfig | 15 LiteX CSR access and provides common litex_[read|write]*
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| /linux-6.3-rc2/Documentation/devicetree/bindings/pci/ |
| A D | snps,dw-pcie.yaml | 96 Vendor-specific CSR names. Consider using the generic names above
99 - description: See native 'elbi/app' CSR region for details.
101 - description: See native 'atu' CSR region for details.
103 - description: Syscon-related CSR regions.
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| A D | altera-pcie-msi.txt | 8 "csr": CSR registers
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| A D | snps,dw-pcie-ep.yaml | 99 Vendor-specific CSR names. Consider using the generic names above
102 - description: See native 'elbi/app' CSR region for details.
104 - description: See native 'atu' CSR region for details.
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| A D | snps,dw-pcie-common.yaml | 22 DWC PCIe CSR space is normally accessed over the dedicated Data Bus
155 - description: Controller Non-sticky CSR flags reset
157 - description: Controller sticky CSR flags reset
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| /linux-6.3-rc2/Documentation/devicetree/bindings/soc/litex/ |
| A D | litex,soc-controller.yaml | 12 Its purpose is to verify LiteX CSR (Control&Status Register) access
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| /linux-6.3-rc2/arch/arm/mach-omap1/ |
| A D | dma.c | 59 [CSR] = { 0x0006, 0x40, OMAP_DMA_REG_16BIT },
219 l = dma_read(CSR, lch); in omap1_clear_dma()
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| A D | omap-dma.c | 87 p->dma_read(CSR, lch); in omap_disable_channel_irq()
325 p->dma_read(CSR, lch); in omap_enable_channel_irq()
711 csr = p->dma_read(CSR, ch); in omap1_dma_handle_ch()
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| /linux-6.3-rc2/Documentation/loongarch/ |
| A D | irq-chip-model.rst | 149 - CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described
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| /linux-6.3-rc2/arch/arm/mach-omap2/ |
| A D | dma.c | 57 [CSR] = { 0x008c, 0x60, OMAP_DMA_REG_32BIT },
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| /linux-6.3-rc2/Documentation/devicetree/bindings/misc/ |
| A D | idt,89hpesx.yaml | 7 title: EEPROM / CSR SMBus-slave interface of IDT 89HPESx devices
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| /linux-6.3-rc2/Documentation/devicetree/bindings/timer/ |
| A D | riscv,timer.yaml | 14 based on the time CSR defined by the RISC-V privileged specification. The
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| /linux-6.3-rc2/Documentation/devicetree/bindings/pinctrl/ |
| A D | pinctrl-sirf.txt | 1 CSR SiRFprimaII pinmux controller
|