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Searched refs:DCN_BASE__INST0_SEG4 (Results 1 – 15 of 15) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/amd/display/dmub/src/
A Ddmub_dcn315.c37 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
A Ddmub_dcn316.c37 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/gpio/dcn315/
A Dhw_factory_dcn315.c49 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
A Dhw_translate_dcn315.c42 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/irq/dcn315/
A Dirq_service_dcn315.c42 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
/linux-6.3-rc2/drivers/gpu/drm/amd/include/
A Dnavi10_ip_offset.h271 #define DCN_BASE__INST0_SEG4 0 macro
A Ddimgrey_cavefish_ip_offset.h367 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
A Dsienna_cichlid_ip_offset.h374 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
A Dbeige_goby_ip_offset.h445 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
A Dvega10_ip_offset.h309 #define DCN_BASE__INST0_SEG4 0 macro
A Drenoir_ip_offset.h1373 #define DCN_BASE__INST0_SEG4 0 macro
A Dvangogh_ip_offset.h456 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
A Dyellow_carp_offset.h391 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn316/
A Ddcn316_resource.c98 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn315/
A Ddcn315_resource.c100 #define DCN_BASE__INST0_SEG4 0x02403C00 macro

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