/linux-6.3-rc2/Documentation/devicetree/bindings/mips/brcm/ |
A D | soc.txt | 45 independently (control registers, DDR PHYs, etc.). One might consider 58 the entire memory controller (including all sub nodes: DDR PHY, 86 == DDR PHY control 88 Control registers for this memory controller's DDR PHY. 95 - reg : the DDR PHY register range and length 104 == DDR memory controller sequencer 106 Control registers for this memory controller's DDR memory sequencer 115 - reg : the DDR sequencer register range and length 136 - reg : the DDR Arbiter register range and length
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/linux-6.3-rc2/Documentation/driver-api/thermal/ |
A D | intel_dptf.rst | 202 are met: there is strong RFI interference because of DDR; CPU power 203 management has no other restriction in changing DDR data rates; 205 DDR-RFIM) for Wi-Fi from BIOS. 239 Request the restriction of specific DDR data rate and set this 247 Restricted DDR data rate for RFI protection: Lower Limit 250 Restricted DDR data rate for RFI protection: Upper Limit 253 DDR data rate selection 1st point 256 DDR data rate selection 2nd point 259 DDR data rate selection 3rd point 262 DDR data rate selection 4th point [all …]
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/linux-6.3-rc2/Documentation/admin-guide/perf/ |
A D | meson-ddr-pmu.rst | 4 Amlogic SoC DDR Bandwidth Performance Monitoring Unit (PMU) 10 to show if the performance bottleneck is on DDR bandwidth. 24 Below are DDR access request event filter keywords: 55 + Show the total DDR bandwidth per seconds: 62 + Show individual DDR bandwidth from CPU and GPU respectively, as well as
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A D | alibaba_pmu.rst | 9 DDR Sub-System Driveway (DRW) PMU Driver 14 channel is split into two independent sub-channels. The DDR Sub-System Driveway 43 The DDR Controller (DDRCTL) and DDR PHY combine to create a complete solution 44 for connecting an SoC application bus to DDR memory devices. The DDRCTL 49 the DDR PHY Interface (DFI) to the PHY module, which launches and captures data
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/linux-6.3-rc2/Documentation/ABI/testing/ |
A D | sysfs-driver-bd9571mwv-regulator | 5 Description: Read/write the current state of DDR Backup Mode, which controls 6 if DDR power rails will be kept powered during system suspend. 10 A. With a momentary power switch (or pulse signal), DDR 26 DDR Backup Mode must be explicitly enabled by the user,
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A D | sysfs-platform-brcmstb-memc | 7 internal DDR controller clock cycles. Possible values range 15 DDR PHY frequency in Hz.
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/linux-6.3-rc2/Documentation/devicetree/bindings/clock/ |
A D | mvebu-core-clock.txt | 12 4 = dramclk (DDR clock) 18 3 = ddrclk (DDR clock) 24 3 = ddrclk (DDR clock) 37 2 = ddrclk (DDR clock) 44 3 = ddrclk (DDR controller clock derived from CPU0 clock) 49 2 = ddrclk (DDR controller clock derived from CPU0 clock)
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/linux-6.3-rc2/Documentation/devicetree/bindings/memory-controllers/ |
A D | snps,dw-umctl2-ddrc.yaml | 15 Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of 20 For instance the ZynqMP DDR controller is based on the DW uMCTL2 v2.40a 28 description: Synopsys DW uMCTL2 DDR controller v3.80a 30 - description: Synopsys DW uMCTL2 DDR controller 32 - description: Xilinx ZynqMP DDR controller v2.40a
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A D | qca,ath79-ddr-controller.yaml | 7 title: Qualcomm Atheros AR7xxx/AR9xxx DDR controller 13 The DDR controller of the AR7xxx and AR9xxx families provides an interface to 14 flush the FIFO between various devices and the DDR. This is mainly used by
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A D | rockchip,rk3399-dmc.yaml | 20 Node to get DDR loading. Refer to 44 The CPU interrupt number. It should be a DCF interrupt. When DDR DVFS 108 Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less 116 Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency 131 frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq, 179 frequency in Hz. When DDR frequency is less then ddr3_odt_dis_freq, the 226 frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq, 318 Defines the power-down idle disable frequency in Hz. When the DDR 324 Defines the self-refresh idle disable frequency in Hz. When the DDR 331 frequency in Hz. When the DDR frequency is greater than [all …]
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A D | xlnx,zynq-ddrc-a05.yaml | 7 title: Zynq A05 DDR Memory Controller 15 The Zynq DDR ECC controller has an optional ECC support in half-bus width
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A D | calxeda-ddr-ctrlr.yaml | 7 title: Calxeda DDR memory controller 10 The Calxeda DDR memory controller is initialised and programmed by the
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A D | renesas,dbsc.yaml | 7 title: Renesas DDR Bus Controllers 15 different names, e.g. "DDR Bus Controller (DBSC)", "DDR3 Bus State Controller
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/linux-6.3-rc2/drivers/gpio/ |
A D | gpio-mb86s7x.c | 31 #define DDR(x) (0x10 + x / 8 * 4) macro 83 val = readl(gchip->base + DDR(gpio)); in mb86s70_gpio_direction_input() 85 writel(val, gchip->base + DDR(gpio)); in mb86s70_gpio_direction_input() 108 val = readl(gchip->base + DDR(gpio)); in mb86s70_gpio_direction_output() 110 writel(val, gchip->base + DDR(gpio)); in mb86s70_gpio_direction_output()
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/linux-6.3-rc2/Documentation/devicetree/bindings/arm/bcm/ |
A D | brcm,brcmstb.txt | 148 independently (control registers, DDR PHYs, etc.). One might consider 163 == DDR PHY control 165 Control registers for this memory controller's DDR PHY. 175 - reg : the DDR PHY register range 177 == DDR SHIMPHY 179 Control registers for this memory controller's DDR SHIMPHY. 183 - reg : the DDR SHIMPHY register range 185 == MEMC DDR control
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/linux-6.3-rc2/drivers/perf/amlogic/ |
A D | Kconfig | 3 tristate "Amlogic DDR Bandwidth Performance Monitor" 6 Provides support for the DDR performance monitor
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/linux-6.3-rc2/drivers/memory/ |
A D | Kconfig | 11 for DRAM (SDR, DDR), ROM, SRAM and others. The drivers features 17 config DDR config 20 Data from JEDEC specs for DDR SDRAM memories, 23 DDR SDRAM controllers. 34 bool "Atmel (Multi-port DDR-)SDRAM Controller" 40 DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs. 41 Starting with the at91sam9g45, this controller supports SDR, DDR and 42 LP-DDR memories. 63 STB SoCs. The firmware running on the DCPU inside the DDR PHY can 104 select DDR
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/linux-6.3-rc2/drivers/mtd/lpddr/ |
A D | Kconfig | 10 flash chips. Synonymous with Mobile-DDR. It is a new standard for 11 DDR memories, intended for battery-operated systems.
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/linux-6.3-rc2/arch/arm/mach-omap2/ |
A D | sleep24xx.S | 55 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished 75 movs r0, r0 @ see if DDR or SDR
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/linux-6.3-rc2/Documentation/devicetree/bindings/perf/ |
A D | amlogic,g12-ddr-pmu.yaml | 7 title: Amlogic G12 DDR performance monitor 13 Amlogic G12 series SoC integrate DDR bandwidth monitor.
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/linux-6.3-rc2/Documentation/devicetree/bindings/pinctrl/ |
A D | fsl,imx7ulp-pinctrl.txt | 4 ports and IOMUXC DDR for DDR interface.
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/linux-6.3-rc2/drivers/perf/ |
A D | Kconfig | 113 tristate "Freescale i.MX8 DDR perf monitor" 116 Provides support for the DDR performance monitor in i.MX8, which 187 tristate "Alibaba T-Head Yitian 710 DDR Sub-system Driveway PMU driver" 190 Support for Driveway PMU events monitoring on Yitian 710 DDR 199 Enable perf support for Marvell DDR Performance monitoring
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/linux-6.3-rc2/Documentation/devicetree/bindings/memory-controllers/fsl/ |
A D | imx8m-ddrc.yaml | 7 title: i.MX8M DDR Controller 13 The DDRC block is integrated in i.MX8M for interfacing with DDR based
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/linux-6.3-rc2/Documentation/driver-api/memory-devices/ |
A D | ti-emif.rst | 38 DDR device details and other board dependent and SoC dependent 41 - DDR device details: 'struct ddr_device_info'
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/linux-6.3-rc2/Documentation/devicetree/bindings/memory-controllers/ddr/ |
A D | jedec,lpddr3-timings.yaml | 19 Maximum DDR clock frequency for the speed-bin, in Hz. 26 Maximum DDR clock frequency for the speed-bin, in Hz. 31 Minimum DDR clock frequency for the speed-bin, in Hz.
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