Searched refs:DISP_CC_MDSS_CORE_BCR (Results 1 – 19 of 19) sorted by relevance
| /linux-6.3-rc2/include/dt-bindings/clock/ |
| A D | qcom,sm6375-dispcc.h | 36 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| A D | qcom,dispcc-sm8150.h | 70 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| A D | qcom,dispcc-sm8250.h | 70 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| A D | qcom,dispcc-sm8350.h | 70 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| A D | qcom,dispcc-sc8280xp.h | 93 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| A D | qcom,sm8450-dispcc.h | 95 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| A D | qcom,sm8550-dispcc.h | 93 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| /linux-6.3-rc2/Documentation/devicetree/bindings/display/msm/ |
| A D | qcom,sc8280xp-mdss.yaml | 73 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
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| A D | qcom,sm8350-mdss.yaml | 90 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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| A D | qcom,sm8450-mdss.yaml | 82 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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| /linux-6.3-rc2/drivers/clk/qcom/ |
| A D | dispcc-sm6375.c | 544 [DISP_CC_MDSS_CORE_BCR] = { 0x1000 },
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| A D | dispcc-sm8250.c | 1219 [DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
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| A D | dispcc-sm8450.c | 1731 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
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| A D | dispcc-sm8550.c | 1716 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
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| A D | dispcc-sc8280xp.c | 3047 [DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
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| /linux-6.3-rc2/arch/arm64/boot/dts/qcom/ |
| A D | sc8280xp.dtsi | 3128 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
4233 resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>;
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| A D | sm8350.dtsi | 2326 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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| A D | sm8550.dtsi | 2099 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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| A D | sm8450.dtsi | 2699 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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