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Searched refs:DISP_CC_MDSS_VSYNC_CLK (Results 1 – 25 of 57) sorted by relevance

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/linux-6.3-rc2/Documentation/devicetree/bindings/display/msm/
A Dqcom,sm8150-dpu.yaml61 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
64 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
A Dqcom,sm8250-dpu.yaml68 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
71 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
A Dqcom,sc8280xp-dpu.yaml70 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
79 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
A Dqcom,sm8350-dpu.yaml67 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
75 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
A Dqcom,sm8450-dpu.yaml74 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
82 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
A Dqcom,sc8280xp-mdss.yaml100 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
108 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
A Dqcom,sm8350-mdss.yaml119 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
127 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
A Dqcom,sm8150-mdss.yaml115 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
118 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
A Dqcom,sm8250-mdss.yaml117 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
120 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
A Dqcom,sm8450-mdss.yaml113 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
121 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
A Dqcom,sm6115-dpu.yaml72 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
/linux-6.3-rc2/include/dt-bindings/clock/
A Dqcom,dispcc-qcm2290.h25 #define DISP_CC_MDSS_VSYNC_CLK 15 macro
A Dqcom,sm6115-dispcc.h28 #define DISP_CC_MDSS_VSYNC_CLK 18 macro
A Dqcom,sm6375-dispcc.h30 #define DISP_CC_MDSS_VSYNC_CLK 19 macro
A Dqcom,dispcc-sm6125.h34 #define DISP_CC_MDSS_VSYNC_CLK 25 macro
A Dqcom,dispcc-sc7180.h39 #define DISP_CC_MDSS_VSYNC_CLK 30 macro
A Dqcom,dispcc-sm6350.h40 #define DISP_CC_MDSS_VSYNC_CLK 29 macro
A Dqcom,dispcc-sdm845.h33 #define DISP_CC_MDSS_VSYNC_CLK 23 macro
A Dqcom,dispcc-sc7280.h47 #define DISP_CC_MDSS_VSYNC_CLK 37 macro
A Dqcom,dispcc-sm8150.h54 #define DISP_CC_MDSS_VSYNC_CLK 44 macro
A Dqcom,dispcc-sm8250.h54 #define DISP_CC_MDSS_VSYNC_CLK 44 macro
A Dqcom,dispcc-sm8350.h54 #define DISP_CC_MDSS_VSYNC_CLK 44 macro
A Dqcom,dispcc-sc8280xp.h85 #define DISP_CC_MDSS_VSYNC_CLK 75 macro
A Dqcom,sm8450-dispcc.h85 #define DISP_CC_MDSS_VSYNC_CLK 75 macro
A Dqcom,sm8550-dispcc.h83 #define DISP_CC_MDSS_VSYNC_CLK 73 macro

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