1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (c) 2006, Intel Corporation.
4 *
5 * Copyright (C) Ashok Raj <ashok.raj@intel.com>
6 * Copyright (C) Shaohua Li <shaohua.li@intel.com>
7 */
8
9 #ifndef __DMAR_H__
10 #define __DMAR_H__
11
12 #include <linux/acpi.h>
13 #include <linux/types.h>
14 #include <linux/msi.h>
15 #include <linux/irqreturn.h>
16 #include <linux/rwsem.h>
17 #include <linux/rculist.h>
18
19 struct acpi_dmar_header;
20
21 #define DMAR_UNITS_SUPPORTED 1024
22
23 /* DMAR Flags */
24 #define DMAR_INTR_REMAP 0x1
25 #define DMAR_X2APIC_OPT_OUT 0x2
26 #define DMAR_PLATFORM_OPT_IN 0x4
27
28 struct intel_iommu;
29
30 struct dmar_dev_scope {
31 struct device __rcu *dev;
32 u8 bus;
33 u8 devfn;
34 };
35
36 #ifdef CONFIG_DMAR_TABLE
37 extern struct acpi_table_header *dmar_tbl;
38 struct dmar_drhd_unit {
39 struct list_head list; /* list of drhd units */
40 struct acpi_dmar_header *hdr; /* ACPI header */
41 u64 reg_base_addr; /* register base address*/
42 unsigned long reg_size; /* size of register set */
43 struct dmar_dev_scope *devices;/* target device array */
44 int devices_cnt; /* target device count */
45 u16 segment; /* PCI domain */
46 u8 ignored:1; /* ignore drhd */
47 u8 include_all:1;
48 u8 gfx_dedicated:1; /* graphic dedicated */
49 struct intel_iommu *iommu;
50 };
51
52 struct dmar_pci_path {
53 u8 bus;
54 u8 device;
55 u8 function;
56 };
57
58 struct dmar_pci_notify_info {
59 struct pci_dev *dev;
60 unsigned long event;
61 int bus;
62 u16 seg;
63 u16 level;
64 struct dmar_pci_path path[];
65 } __attribute__((packed));
66
67 extern struct rw_semaphore dmar_global_lock;
68 extern struct list_head dmar_drhd_units;
69
70 #define for_each_drhd_unit(drhd) \
71 list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \
72 dmar_rcu_check())
73
74 #define for_each_active_drhd_unit(drhd) \
75 list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \
76 dmar_rcu_check()) \
77 if (drhd->ignored) {} else
78
79 #define for_each_active_iommu(i, drhd) \
80 list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \
81 dmar_rcu_check()) \
82 if (i=drhd->iommu, drhd->ignored) {} else
83
84 #define for_each_iommu(i, drhd) \
85 list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \
86 dmar_rcu_check()) \
87 if (i=drhd->iommu, 0) {} else
88
dmar_rcu_check(void)89 static inline bool dmar_rcu_check(void)
90 {
91 return rwsem_is_locked(&dmar_global_lock) ||
92 system_state == SYSTEM_BOOTING;
93 }
94
95 #define dmar_rcu_dereference(p) rcu_dereference_check((p), dmar_rcu_check())
96
97 #define for_each_dev_scope(devs, cnt, i, tmp) \
98 for ((i) = 0; ((tmp) = (i) < (cnt) ? \
99 dmar_rcu_dereference((devs)[(i)].dev) : NULL, (i) < (cnt)); \
100 (i)++)
101
102 #define for_each_active_dev_scope(devs, cnt, i, tmp) \
103 for_each_dev_scope((devs), (cnt), (i), (tmp)) \
104 if (!(tmp)) { continue; } else
105
106 extern int dmar_table_init(void);
107 extern int dmar_dev_scope_init(void);
108 extern void dmar_register_bus_notifier(void);
109 extern int dmar_parse_dev_scope(void *start, void *end, int *cnt,
110 struct dmar_dev_scope **devices, u16 segment);
111 extern void *dmar_alloc_dev_scope(void *start, void *end, int *cnt);
112 extern void dmar_free_dev_scope(struct dmar_dev_scope **devices, int *cnt);
113 extern int dmar_insert_dev_scope(struct dmar_pci_notify_info *info,
114 void *start, void*end, u16 segment,
115 struct dmar_dev_scope *devices,
116 int devices_cnt);
117 extern int dmar_remove_dev_scope(struct dmar_pci_notify_info *info,
118 u16 segment, struct dmar_dev_scope *devices,
119 int count);
120 /* Intel IOMMU detection */
121 void detect_intel_iommu(void);
122 extern int enable_drhd_fault_handling(void);
123 extern int dmar_device_add(acpi_handle handle);
124 extern int dmar_device_remove(acpi_handle handle);
125
dmar_res_noop(struct acpi_dmar_header * hdr,void * arg)126 static inline int dmar_res_noop(struct acpi_dmar_header *hdr, void *arg)
127 {
128 return 0;
129 }
130
131 #ifdef CONFIG_DMAR_DEBUG
132 void dmar_fault_dump_ptes(struct intel_iommu *iommu, u16 source_id,
133 unsigned long long addr, u32 pasid);
134 #else
dmar_fault_dump_ptes(struct intel_iommu * iommu,u16 source_id,unsigned long long addr,u32 pasid)135 static inline void dmar_fault_dump_ptes(struct intel_iommu *iommu, u16 source_id,
136 unsigned long long addr, u32 pasid) {}
137 #endif
138
139 #ifdef CONFIG_INTEL_IOMMU
140 extern int iommu_detected, no_iommu;
141 extern int intel_iommu_init(void);
142 extern void intel_iommu_shutdown(void);
143 extern int dmar_parse_one_rmrr(struct acpi_dmar_header *header, void *arg);
144 extern int dmar_parse_one_atsr(struct acpi_dmar_header *header, void *arg);
145 extern int dmar_check_one_atsr(struct acpi_dmar_header *hdr, void *arg);
146 extern int dmar_parse_one_satc(struct acpi_dmar_header *hdr, void *arg);
147 extern int dmar_release_one_atsr(struct acpi_dmar_header *hdr, void *arg);
148 extern int dmar_iommu_hotplug(struct dmar_drhd_unit *dmaru, bool insert);
149 extern int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info);
150 #else /* !CONFIG_INTEL_IOMMU: */
intel_iommu_init(void)151 static inline int intel_iommu_init(void) { return -ENODEV; }
intel_iommu_shutdown(void)152 static inline void intel_iommu_shutdown(void) { }
153
154 #define dmar_parse_one_rmrr dmar_res_noop
155 #define dmar_parse_one_atsr dmar_res_noop
156 #define dmar_check_one_atsr dmar_res_noop
157 #define dmar_release_one_atsr dmar_res_noop
158 #define dmar_parse_one_satc dmar_res_noop
159
dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info * info)160 static inline int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info)
161 {
162 return 0;
163 }
164
dmar_iommu_hotplug(struct dmar_drhd_unit * dmaru,bool insert)165 static inline int dmar_iommu_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
166 {
167 return 0;
168 }
169 #endif /* CONFIG_INTEL_IOMMU */
170
171 #ifdef CONFIG_IRQ_REMAP
172 extern int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert);
173 #else /* CONFIG_IRQ_REMAP */
dmar_ir_hotplug(struct dmar_drhd_unit * dmaru,bool insert)174 static inline int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
175 { return 0; }
176 #endif /* CONFIG_IRQ_REMAP */
177
178 extern bool dmar_platform_optin(void);
179
180 #else /* CONFIG_DMAR_TABLE */
181
dmar_device_add(void * handle)182 static inline int dmar_device_add(void *handle)
183 {
184 return 0;
185 }
186
dmar_device_remove(void * handle)187 static inline int dmar_device_remove(void *handle)
188 {
189 return 0;
190 }
191
dmar_platform_optin(void)192 static inline bool dmar_platform_optin(void)
193 {
194 return false;
195 }
196
detect_intel_iommu(void)197 static inline void detect_intel_iommu(void)
198 {
199 }
200
201 #endif /* CONFIG_DMAR_TABLE */
202
203 struct irte {
204 union {
205 /* Shared between remapped and posted mode*/
206 struct {
207 __u64 present : 1, /* 0 */
208 fpd : 1, /* 1 */
209 __res0 : 6, /* 2 - 6 */
210 avail : 4, /* 8 - 11 */
211 __res1 : 3, /* 12 - 14 */
212 pst : 1, /* 15 */
213 vector : 8, /* 16 - 23 */
214 __res2 : 40; /* 24 - 63 */
215 };
216
217 /* Remapped mode */
218 struct {
219 __u64 r_present : 1, /* 0 */
220 r_fpd : 1, /* 1 */
221 dst_mode : 1, /* 2 */
222 redir_hint : 1, /* 3 */
223 trigger_mode : 1, /* 4 */
224 dlvry_mode : 3, /* 5 - 7 */
225 r_avail : 4, /* 8 - 11 */
226 r_res0 : 4, /* 12 - 15 */
227 r_vector : 8, /* 16 - 23 */
228 r_res1 : 8, /* 24 - 31 */
229 dest_id : 32; /* 32 - 63 */
230 };
231
232 /* Posted mode */
233 struct {
234 __u64 p_present : 1, /* 0 */
235 p_fpd : 1, /* 1 */
236 p_res0 : 6, /* 2 - 7 */
237 p_avail : 4, /* 8 - 11 */
238 p_res1 : 2, /* 12 - 13 */
239 p_urgent : 1, /* 14 */
240 p_pst : 1, /* 15 */
241 p_vector : 8, /* 16 - 23 */
242 p_res2 : 14, /* 24 - 37 */
243 pda_l : 26; /* 38 - 63 */
244 };
245 __u64 low;
246 };
247
248 union {
249 /* Shared between remapped and posted mode*/
250 struct {
251 __u64 sid : 16, /* 64 - 79 */
252 sq : 2, /* 80 - 81 */
253 svt : 2, /* 82 - 83 */
254 __res3 : 44; /* 84 - 127 */
255 };
256
257 /* Posted mode*/
258 struct {
259 __u64 p_sid : 16, /* 64 - 79 */
260 p_sq : 2, /* 80 - 81 */
261 p_svt : 2, /* 82 - 83 */
262 p_res3 : 12, /* 84 - 95 */
263 pda_h : 32; /* 96 - 127 */
264 };
265 __u64 high;
266 };
267 };
268
dmar_copy_shared_irte(struct irte * dst,struct irte * src)269 static inline void dmar_copy_shared_irte(struct irte *dst, struct irte *src)
270 {
271 dst->present = src->present;
272 dst->fpd = src->fpd;
273 dst->avail = src->avail;
274 dst->pst = src->pst;
275 dst->vector = src->vector;
276 dst->sid = src->sid;
277 dst->sq = src->sq;
278 dst->svt = src->svt;
279 }
280
281 #define PDA_LOW_BIT 26
282 #define PDA_HIGH_BIT 32
283
284 /* Can't use the common MSI interrupt functions
285 * since DMAR is not a pci device
286 */
287 struct irq_data;
288 extern void dmar_msi_unmask(struct irq_data *data);
289 extern void dmar_msi_mask(struct irq_data *data);
290 extern void dmar_msi_read(int irq, struct msi_msg *msg);
291 extern void dmar_msi_write(int irq, struct msi_msg *msg);
292 extern int dmar_set_interrupt(struct intel_iommu *iommu);
293 extern irqreturn_t dmar_fault(int irq, void *dev_id);
294 extern int dmar_alloc_hwirq(int id, int node, void *arg);
295 extern void dmar_free_hwirq(int irq);
296
297 #endif /* __DMAR_H__ */
298