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Searched refs:DPIO_PHY0 (Results 1 – 11 of 11) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/i915/
A Dintel_gvt_mmio_table.c1118 MMIO_D(BXT_PHY_CTL_FAMILY(DPIO_PHY0)); in iterate_bxt_mmio()
1126 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0)); in iterate_bxt_mmio()
1127 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0)); in iterate_bxt_mmio()
1128 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0)); in iterate_bxt_mmio()
1129 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0)); in iterate_bxt_mmio()
1130 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0)); in iterate_bxt_mmio()
1131 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0)); in iterate_bxt_mmio()
1132 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0)); in iterate_bxt_mmio()
1133 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0)); in iterate_bxt_mmio()
1134 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0)); in iterate_bxt_mmio()
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A Dvlv_sideband.c225 return phy == DPIO_PHY0 ? IOSF_PORT_DPIO_2 : IOSF_PORT_DPIO; in vlv_dpio_phy_iosf_port()
A Di915_reg.h1459 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30))
/linux-6.3-rc2/drivers/gpu/drm/i915/display/
A Dintel_display_power_well.c1317 if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY0]) in assert_chv_phy_status()
1319 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | in assert_chv_phy_status()
1320 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | in assert_chv_phy_status()
1321 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | in assert_chv_phy_status()
1322 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | in assert_chv_phy_status()
1323 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); in assert_chv_phy_status()
1331 phy_status |= PHY_POWERGOOD(DPIO_PHY0); in assert_chv_phy_status()
1344 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); in assert_chv_phy_status()
1420 phy = DPIO_PHY0; in chv_dpio_cmn_power_well_enable()
1483 phy = DPIO_PHY0; in chv_dpio_cmn_power_well_disable()
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A Dintel_dpio_phy.c165 [DPIO_PHY0] = {
187 [DPIO_PHY0] = {
268 *phy = DPIO_PHY0; in bxt_port_to_phy_channel()
682 return DPIO_PHY0; in vlv_dig_port_to_phy()
862 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); in chv_phy_pre_pll_enable()
1010 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); in chv_phy_release_cl2_override()
A Dintel_display_power.c1732 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | in chv_phy_control_init()
1734 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | in chv_phy_control_init()
1735 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) | in chv_phy_control_init()
1754 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); in chv_phy_control_init()
1757 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); in chv_phy_control_init()
1764 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1); in chv_phy_control_init()
1767 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); in chv_phy_control_init()
1769 dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); in chv_phy_control_init()
1771 dev_priv->display.power.chv_phy_assert[DPIO_PHY0] = false; in chv_phy_control_init()
1773 dev_priv->display.power.chv_phy_assert[DPIO_PHY0] = true; in chv_phy_control_init()
A Dintel_dpio_phy.h24 DPIO_PHY0, enumerator
A Dintel_display_power_map.c483 .bxt.phy = DPIO_PHY0,
587 .bxt.phy = DPIO_PHY0,
/linux-6.3-rc2/drivers/gpu/drm/i915/gvt/
A Ddisplay.c235 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= in emulate_monitor_status_change()
239 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30); in emulate_monitor_status_change()
298 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= in emulate_monitor_status_change()
300 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= in emulate_monitor_status_change()
328 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= in emulate_monitor_status_change()
330 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= in emulate_monitor_status_change()
A Dmmio.c264 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= in intel_vgpu_reset_mmio()
268 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= in intel_vgpu_reset_mmio()
A Dhandlers.c534 enum dpio_phy phy = DPIO_PHY0; in bxt_vgpu_get_dp_bitrate()
546 phy = DPIO_PHY0; in bxt_vgpu_get_dp_bitrate()
550 phy = DPIO_PHY0; in bxt_vgpu_get_dp_bitrate()
1874 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= in bxt_gt_disp_pwron_write()
1876 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= in bxt_gt_disp_pwron_write()
2749 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT, in init_bxt_mmio_info()
2760 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT, in init_bxt_mmio_info()
2762 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT, in init_bxt_mmio_info()
2764 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT, in init_bxt_mmio_info()
2766 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT, in init_bxt_mmio_info()

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