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Searched refs:DPMTABLE_OD_UPDATE_MCLK (Results 1 – 12 of 12) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/radeon/
A Dci_dpm.h190 #define DPMTABLE_OD_UPDATE_MCLK 0x00000002 macro
A Dci_dpm.c1433 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { in ci_unfreeze_sclk_mclk_dpm()
1541 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { in ci_freeze_sclk_mclk_dpm()
3851 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3874 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) in ci_populate_and_upload_sclk_mclk_dpm_levels()
3883 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { in ci_populate_and_upload_sclk_mclk_dpm_levels()
4734 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) in ci_update_and_upload_mc_reg_table()
/linux-6.3-rc2/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dvega12_hwmgr.h176 #define DPMTABLE_OD_UPDATE_MCLK 0x00000002 macro
A Dvega20_hwmgr.h229 #define DPMTABLE_OD_UPDATE_MCLK 0x00000002 macro
A Dsmu7_hwmgr.c1030 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; in smu7_check_dpm_table_updated()
1040 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK; in smu7_check_dpm_table_updated()
1055 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK; in smu7_check_dpm_table_updated()
4113 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; in smu7_find_dpm_states_clocks_in_dpm_table()
4221 DPMTABLE_OD_UPDATE_MCLK)) { in smu7_freeze_sclk_mclk_dpm()
4256 if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { in smu7_populate_and_upload_sclk_mclk_dpm_levels()
4272 (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { in smu7_populate_and_upload_sclk_mclk_dpm_levels()
4377 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { in smu7_unfreeze_sclk_mclk_dpm()
4736 DPMTABLE_OD_UPDATE_MCLK | in smu7_check_states_equal()
A Dvega10_hwmgr.c1832 if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { in vega10_populate_single_memory_level()
2527 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK; in vega10_check_dpm_table_updated()
2570 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK; in vega10_init_smc_table()
3447 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; in vega10_find_dpm_states_clocks_in_dpm_table()
3477 if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { in vega10_populate_and_upload_sclk_mclk_dpm_levels()
3491 (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { in vega10_populate_and_upload_sclk_mclk_dpm_levels()
5555 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; in vega10_odn_edit_dpm_table()
/linux-6.3-rc2/drivers/gpu/drm/amd/pm/powerplay/inc/
A Dhardwaremanager.h378 #define DPMTABLE_OD_UPDATE_MCLK 0x00000002 macro
/linux-6.3-rc2/drivers/gpu/drm/amd/pm/powerplay/smumgr/
A Diceland_smumgr.c1782 if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) in iceland_update_and_upload_mc_reg_table()
2168 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK)) in iceland_program_mem_timing_parameters()
A Dci_smumgr.c1817 if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) in ci_update_and_upload_mc_reg_table()
2205 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK)) in ci_program_mem_timing_parameters()
A Dtonga_smumgr.c2161 if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) in tonga_update_and_upload_mc_reg_table()
2557 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK)) in tonga_program_mem_timing_parameters()
A Dfiji_smumgr.c2255 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK)) in fiji_program_mem_timing_parameters()
A Dpolaris10_smumgr.c2139 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK)) in polaris10_program_mem_timing_parameters()

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