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Searched refs:DPU_REG_WRITE (Results 1 – 14 of 14) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_hw_util.c160 DPU_REG_WRITE(c, in _dpu_hw_setup_scaler3_lut()
212 DPU_REG_WRITE(c, in _dpu_hw_setup_scaler3lite_lut()
388 DPU_REG_WRITE(c, csc_reg_off, val); in dpu_hw_csc_setup()
391 DPU_REG_WRITE(c, csc_reg_off + 0x4, val); in dpu_hw_csc_setup()
394 DPU_REG_WRITE(c, csc_reg_off + 0x8, val); in dpu_hw_csc_setup()
397 DPU_REG_WRITE(c, csc_reg_off + 0xc, val); in dpu_hw_csc_setup()
399 DPU_REG_WRITE(c, csc_reg_off + 0x10, val); in dpu_hw_csc_setup()
403 DPU_REG_WRITE(c, csc_reg_off + 0x14, val); in dpu_hw_csc_setup()
405 DPU_REG_WRITE(c, csc_reg_off + 0x18, val); in dpu_hw_csc_setup()
407 DPU_REG_WRITE(c, csc_reg_off + 0x1c, val); in dpu_hw_csc_setup()
[all …]
A Ddpu_hw_dsc.c38 DPU_REG_WRITE(c, DSC_COMMON_MODE, 0); in dpu_hw_dsc_disable()
52 DPU_REG_WRITE(c, DSC_COMMON_MODE, mode); in dpu_hw_dsc_config()
68 DPU_REG_WRITE(c, DSC_ENC, data); in dpu_hw_dsc_config()
72 DPU_REG_WRITE(c, DSC_PICTURE, data); in dpu_hw_dsc_config()
76 DPU_REG_WRITE(c, DSC_SLICE, data); in dpu_hw_dsc_config()
79 DPU_REG_WRITE(c, DSC_CHUNK_SIZE, data); in dpu_hw_dsc_config()
83 DPU_REG_WRITE(c, DSC_DELAY, data); in dpu_hw_dsc_config()
99 DPU_REG_WRITE(c, DSC_BPG_OFFSET, data); in dpu_hw_dsc_config()
103 DPU_REG_WRITE(c, DSC_DSC_OFFSET, data); in dpu_hw_dsc_config()
109 DPU_REG_WRITE(c, DSC_FLATNESS, data); in dpu_hw_dsc_config()
[all …]
A Ddpu_hw_wb.c127 DPU_REG_WRITE(c, WB_ALPHA_X_VALUE, 0xFF); in dpu_hw_wb_setup_format()
128 DPU_REG_WRITE(c, WB_DST_FORMAT, dst_format); in dpu_hw_wb_setup_format()
129 DPU_REG_WRITE(c, WB_DST_OP_MODE, opmode); in dpu_hw_wb_setup_format()
131 DPU_REG_WRITE(c, WB_DST_YSTRIDE0, ystride0); in dpu_hw_wb_setup_format()
132 DPU_REG_WRITE(c, WB_DST_YSTRIDE1, ystride1); in dpu_hw_wb_setup_format()
133 DPU_REG_WRITE(c, WB_OUT_SIZE, outsize); in dpu_hw_wb_setup_format()
148 DPU_REG_WRITE(c, WB_OUT_XY, out_xy); in dpu_hw_wb_roi()
149 DPU_REG_WRITE(c, WB_OUT_SIZE, out_size); in dpu_hw_wb_roi()
178 DPU_REG_WRITE(c, WB_QOS_CTRL, qos_ctrl); in dpu_hw_wb_setup_qos_lut()
199 DPU_REG_WRITE(c, WB_CDP_CNTL, cdp_cntl); in dpu_hw_wb_setup_cdp()
[all …]
A Ddpu_hw_intf.c219 DPU_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl); in dpu_hw_intf_setup_timing_engine()
221 DPU_REG_WRITE(c, INTF_VSYNC_PULSE_WIDTH_F0, in dpu_hw_intf_setup_timing_engine()
223 DPU_REG_WRITE(c, INTF_DISPLAY_HCTL, display_hctl); in dpu_hw_intf_setup_timing_engine()
226 DPU_REG_WRITE(c, INTF_ACTIVE_HCTL, active_hctl); in dpu_hw_intf_setup_timing_engine()
231 DPU_REG_WRITE(c, INTF_HSYNC_SKEW, p->hsync_skew); in dpu_hw_intf_setup_timing_engine()
233 DPU_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3); in dpu_hw_intf_setup_timing_engine()
234 DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg); in dpu_hw_intf_setup_timing_engine()
237 DPU_REG_WRITE(c, INTF_CONFIG2, intf_cfg2); in dpu_hw_intf_setup_timing_engine()
267 DPU_REG_WRITE(c, INTF_PROG_FETCH_START, in dpu_hw_intf_setup_prg_fetch()
273 DPU_REG_WRITE(c, INTF_CONFIG, fetch_enable); in dpu_hw_intf_setup_prg_fetch()
[all …]
A Ddpu_hw_dspp.c45 DPU_REG_WRITE(&ctx->hw, base, PCC_DIS); in dpu_setup_dspp_pcc()
49 DPU_REG_WRITE(&ctx->hw, base + PCC_RED_R_OFF, cfg->r.r); in dpu_setup_dspp_pcc()
50 DPU_REG_WRITE(&ctx->hw, base + PCC_RED_G_OFF, cfg->r.g); in dpu_setup_dspp_pcc()
51 DPU_REG_WRITE(&ctx->hw, base + PCC_RED_B_OFF, cfg->r.b); in dpu_setup_dspp_pcc()
53 DPU_REG_WRITE(&ctx->hw, base + PCC_GREEN_R_OFF, cfg->g.r); in dpu_setup_dspp_pcc()
54 DPU_REG_WRITE(&ctx->hw, base + PCC_GREEN_G_OFF, cfg->g.g); in dpu_setup_dspp_pcc()
55 DPU_REG_WRITE(&ctx->hw, base + PCC_GREEN_B_OFF, cfg->g.b); in dpu_setup_dspp_pcc()
57 DPU_REG_WRITE(&ctx->hw, base + PCC_BLUE_R_OFF, cfg->b.r); in dpu_setup_dspp_pcc()
58 DPU_REG_WRITE(&ctx->hw, base + PCC_BLUE_G_OFF, cfg->b.g); in dpu_setup_dspp_pcc()
59 DPU_REG_WRITE(&ctx->hw, base + PCC_BLUE_B_OFF, cfg->b.b); in dpu_setup_dspp_pcc()
[all …]
A Ddpu_hw_sspp.c308 DPU_REG_WRITE(c, SSPP_FETCH_CONFIG, in dpu_hw_sspp_setup_format()
314 DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, in dpu_hw_sspp_setup_format()
321 DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, in dpu_hw_sspp_setup_format()
326 DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, in dpu_hw_sspp_setup_format()
331 DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, in dpu_hw_sspp_setup_format()
357 DPU_REG_WRITE(c, op_mode_off + idx, opmode); in dpu_hw_sspp_setup_format()
511 DPU_REG_WRITE(c, src_xy_off + idx, src_xy); in dpu_hw_sspp_setup_rects()
513 DPU_REG_WRITE(c, out_xy_off + idx, dst_xy); in dpu_hw_sspp_setup_rects()
534 DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx, in dpu_hw_sspp_setup_sourceaddress()
536 DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx, in dpu_hw_sspp_setup_sourceaddress()
[all …]
A Ddpu_hw_ctl.c98 DPU_REG_WRITE(&ctx->hw, CTL_START, 0x1); in dpu_hw_ctl_trigger_start()
110 DPU_REG_WRITE(&ctx->hw, CTL_PREPARE, 0x1); in dpu_hw_ctl_trigger_pending()
136 DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH, in dpu_hw_ctl_trigger_flush_v1()
139 DPU_REG_WRITE(&ctx->hw, CTL_INTF_FLUSH, in dpu_hw_ctl_trigger_flush_v1()
142 DPU_REG_WRITE(&ctx->hw, CTL_WB_FLUSH, in dpu_hw_ctl_trigger_flush_v1()
339 DPU_REG_WRITE(c, CTL_SW_RESET, 0x1); in dpu_hw_ctl_reset_control()
373 DPU_REG_WRITE(c, CTL_LAYER(mixer_id), 0); in dpu_hw_ctl_clear_all_blendstages()
500 DPU_REG_WRITE(c, CTL_TOP, mode_sel); in dpu_hw_ctl_intf_cfg_v1()
505 DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, in dpu_hw_ctl_intf_cfg_v1()
543 DPU_REG_WRITE(c, CTL_TOP, intf_cfg); in dpu_hw_ctl_intf_cfg()
[all …]
A Ddpu_hw_pingpong.c72 DPU_REG_WRITE(c, base + PP_DITHER_EN, 0); in dpu_hw_pp_setup_dither()
91 DPU_REG_WRITE(c, base + PP_DITHER_EN, 1); in dpu_hw_pp_setup_dither()
110 DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg); in dpu_hw_pp_setup_te_config()
114 DPU_REG_WRITE(c, PP_START_POS, te->start_pos); in dpu_hw_pp_setup_te_config()
115 DPU_REG_WRITE(c, PP_SYNC_THRESH, in dpu_hw_pp_setup_te_config()
118 DPU_REG_WRITE(c, PP_SYNC_WRCOUNT, in dpu_hw_pp_setup_te_config()
127 DPU_REG_WRITE(&pp->hw, PP_AUTOREFRESH_CONFIG, in dpu_hw_pp_setup_autorefresh_config()
172 DPU_REG_WRITE(c, PP_TEAR_CHECK_EN, enable); in dpu_hw_pp_enable_te()
193 DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg); in dpu_hw_pp_connect_external_te()
252 DPU_REG_WRITE(c, PP_DSC_MODE, 1); in dpu_hw_pp_dsc_enable()
[all …]
A Ddpu_hw_lm.c76 DPU_REG_WRITE(c, LM_OUT_SIZE, outsize); in dpu_hw_lm_setup_out()
83 DPU_REG_WRITE(c, LM_OP_MODE, op_mode); in dpu_hw_lm_setup_out()
93 DPU_REG_WRITE(c, LM_BORDER_COLOR_0, in dpu_hw_lm_setup_border_color()
96 DPU_REG_WRITE(c, LM_BORDER_COLOR_1, in dpu_hw_lm_setup_border_color()
127 DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA + stage_off, const_alpha); in dpu_hw_lm_setup_blend_config_combined_alpha()
128 DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); in dpu_hw_lm_setup_blend_config_combined_alpha()
144 DPU_REG_WRITE(c, LM_BLEND0_FG_ALPHA + stage_off, fg_alpha); in dpu_hw_lm_setup_blend_config()
145 DPU_REG_WRITE(c, LM_BLEND0_BG_ALPHA + stage_off, bg_alpha); in dpu_hw_lm_setup_blend_config()
146 DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); in dpu_hw_lm_setup_blend_config()
160 DPU_REG_WRITE(c, LM_OP_MODE, op_mode); in dpu_hw_lm_setup_color3()
A Ddpu_hw_top.c60 DPU_REG_WRITE(c, SSPP_SPARE, cfg->split_flush_en ? 0x1 : 0x0); in dpu_hw_setup_split_pipe()
61 DPU_REG_WRITE(c, SPLIT_DISPLAY_LOWER_PIPE_CTRL, lower_pipe); in dpu_hw_setup_split_pipe()
62 DPU_REG_WRITE(c, SPLIT_DISPLAY_UPPER_PIPE_CTRL, upper_pipe); in dpu_hw_setup_split_pipe()
63 DPU_REG_WRITE(c, SPLIT_DISPLAY_EN, cfg->en & 0x1); in dpu_hw_setup_split_pipe()
92 DPU_REG_WRITE(c, reg_off, new_val); in dpu_hw_setup_clk_force_ctrl()
150 DPU_REG_WRITE(c, MDP_VSYNC_SEL, reg); in dpu_hw_setup_vsync_source()
183 DPU_REG_WRITE(c, wd_load_value, in dpu_hw_setup_vsync_source()
186 DPU_REG_WRITE(c, wd_ctl, BIT(0)); /* clear timer */ in dpu_hw_setup_vsync_source()
190 DPU_REG_WRITE(c, wd_ctl2, reg); in dpu_hw_setup_vsync_source()
235 DPU_REG_WRITE(c, HDMI_DP_CORE_SELECT, 0x1); in dpu_hw_intf_audio_select()
A Ddpu_hw_vbif.c52 DPU_REG_WRITE(c, VBIF_XIN_CLR_ERR, pnd | src); in dpu_hw_clear_errors()
82 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_mem_type()
103 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_limit_conf()
141 DPU_REG_WRITE(c, VBIF_XIN_HALT_CTRL0, reg_val); in dpu_hw_set_halt_ctrl()
181 DPU_REG_WRITE(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high, reg_val); in dpu_hw_set_qos_remap()
182 DPU_REG_WRITE(c, reg_lvl + reg_high, reg_val_lvl); in dpu_hw_set_qos_remap()
197 DPU_REG_WRITE(c, VBIF_WRITE_GATHER_EN, reg_val); in dpu_hw_set_write_gather_en()
A Ddpu_hw_merge3d.c44 DPU_REG_WRITE(c, MERGE_3D_MODE, 0); in dpu_hw_merge_3d_setup_3d_mode()
45 DPU_REG_WRITE(c, MERGE_3D_MUX, 0); in dpu_hw_merge_3d_setup_3d_mode()
48 DPU_REG_WRITE(c, MERGE_3D_MODE, data); in dpu_hw_merge_3d_setup_3d_mode()
A Ddpu_hw_interrupts.c212 DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, in dpu_core_irq()
279 DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx)); in dpu_hw_intr_enable_irq_locked()
281 DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask); in dpu_hw_intr_enable_irq_locked()
328 DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask); in dpu_hw_intr_disable_irq_locked()
330 DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx)); in dpu_hw_intr_disable_irq_locked()
354 DPU_REG_WRITE(&intr->hw, in dpu_clear_irqs()
372 DPU_REG_WRITE(&intr->hw, in dpu_disable_all_irqs()
408 DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, in dpu_core_irq_read()
A Ddpu_hw_util.h332 #define DPU_REG_WRITE(c, off, val) dpu_reg_write(c, off, val, #off) macro

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