Searched refs:EN0 (Results 1 – 3 of 3) sorted by relevance
312 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + EN0); in ipi_en0_regs_init()314 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + EN0); in ipi_en0_regs_init()316 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + EN0); in ipi_en0_regs_init()318 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + EN0); in ipi_en0_regs_init()320 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + EN0); in ipi_en0_regs_init()322 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + EN0); in ipi_en0_regs_init()324 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + EN0); in ipi_en0_regs_init()326 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + EN0); in ipi_en0_regs_init()328 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + EN0); in ipi_en0_regs_init()330 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + EN0); in ipi_en0_regs_init()[all …]
22 #define EN0 0x04 macro
40 (EN0, EN1), and 3 master sequencing timers called FPS0, FPS1 and FPS2.79 hardware input to PMIC i.e. EN0, EN1 or85 for hardware input pin EN0.
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