Searched refs:EVENT_INDEX (Results 1 – 19 of 19) sorted by relevance
171 #define EVENT_INDEX(x) ((x) << 8) macro180 #define EVENT_INDEX(x) ((x) << 8) macro
154 #define EVENT_INDEX(x) ((x) << 8) macro
156 #define EVENT_INDEX(x) ((x) << 8) macro
228 #define EVENT_INDEX(x) ((x) << 8) macro
346 #define EVENT_INDEX(x) ((x) << 8) macro
2098 EVENT_INDEX(4)); in gfx_v7_0_ring_emit_vgt_flush()2102 EVENT_INDEX(0)); in gfx_v7_0_ring_emit_vgt_flush()2128 EVENT_INDEX(5))); in gfx_v7_0_ring_emit_fence_gfx()2140 EVENT_INDEX(5))); in gfx_v7_0_ring_emit_fence_gfx()2171 EVENT_INDEX(5))); in gfx_v7_0_ring_emit_fence_compute()
1564 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); in gfx_v8_0_do_edc_gpr_workarounds()1590 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); in gfx_v8_0_do_edc_gpr_workarounds()1616 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); in gfx_v8_0_do_edc_gpr_workarounds()6078 EVENT_INDEX(4)); in gfx_v8_0_ring_emit_vgt_flush()6082 EVENT_INDEX(0)); in gfx_v8_0_ring_emit_vgt_flush()6165 EVENT_INDEX(5))); in gfx_v8_0_ring_emit_fence_gfx()6179 EVENT_INDEX(5))); in gfx_v8_0_ring_emit_fence_gfx()6258 EVENT_INDEX(5))); in gfx_v8_0_ring_emit_fence_compute()
1813 #define EVENT_INDEX(x) ((x) << 8) macro
4413 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); in gfx_v9_0_do_edc_gpr_workarounds()4441 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); in gfx_v9_0_do_edc_gpr_workarounds()4469 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); in gfx_v9_0_do_edc_gpr_workarounds()5192 EVENT_INDEX(5); in gfx_v9_0_ring_emit_fence()
1801 EVENT_INDEX(0)); in gfx_v6_0_ring_emit_vgt_flush()1823 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); in gfx_v6_0_ring_emit_fence()
70 #define EVENT_INDEX RESET_COMPLETE macro172 #define CCG_EVENT_MAX (EVENT_INDEX + 43)679 return (code >= CCG_EVENT_MAX) || (code < EVENT_INDEX); in invalid_async_evt()
1240 #define EVENT_INDEX(x) ((x) << 8) macro
1750 #define EVENT_INDEX(x) ((x) << 8) macro
1814 #define EVENT_INDEX(x) ((x) << 8) macro
1405 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); in cayman_fence_ring_emit()
1665 #define EVENT_INDEX(x) ((x) << 8) macro
2887 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); in r600_fence_ring_emit()2900 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); in r600_fence_ring_emit()
3553 EVENT_INDEX(5))); in cik_fence_gfx_ring_emit()3565 EVENT_INDEX(5))); in cik_fence_gfx_ring_emit()3592 EVENT_INDEX(5))); in cik_fence_compute_ring_emit()
3389 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); in si_fence_ring_emit()
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