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Searched refs:GC (Results 1 – 25 of 43) sorted by relevance

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/linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/
A Dgfx_v10_0.c4275 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, in wave_read_ind()
4285 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, in wave_read_regs()
5048 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); in gfx_v10_0_rlc_stop()
6210 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, in gfx_v10_0_cp_compute_enable()
6800 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, in gfx_v10_0_kiq_init_register()
8303 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, in gfx_v10_0_ring_set_wptr_gfx()
9174 tmp = RREG32_SOC15_IP(GC, target); in gfx_v10_0_kiq_set_interrupt_state()
9177 WREG32_SOC15_IP(GC, target, tmp); in gfx_v10_0_kiq_set_interrupt_state()
9184 tmp = RREG32_SOC15_IP(GC, target); in gfx_v10_0_kiq_set_interrupt_state()
9187 WREG32_SOC15_IP(GC, target, tmp); in gfx_v10_0_kiq_set_interrupt_state()
[all …]
A Dimu_v11_0.c100 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, 0); in imu_v11_0_load_microcode()
112 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, 0); in imu_v11_0_load_microcode()
152 WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val); in imu_v11_0_setup()
158 WREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10, imu_reg_val); in imu_v11_0_setup()
166 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL); in imu_v11_0_start()
168 WREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL, imu_reg_val); in imu_v11_0_start()
341 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, data); in program_imu_rlc_ram()
344 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, 0); in program_imu_rlc_ram()
345 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, 0); in program_imu_rlc_ram()
346 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, 0); in program_imu_rlc_ram()
[all …]
A Dimu_v11_0_3.c34 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_MISC2, 0x00001ffe, 0xe0000000),
41 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_MISC, 0x00000017, 0xe0000000),
42 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_ENABLE, 0x00000001, 0xe0000000),
49 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_MAM_CTRL, 0x0000d800, 0xe0000000),
56 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_MISC, 0x0c48bff0, 0xe0000000),
130 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, 0); in program_rlc_ram_register_setting()
131 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, reg); in program_rlc_ram_register_setting()
132 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, data); in program_rlc_ram_register_setting()
135 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, 0); in program_rlc_ram_register_setting()
136 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, 0); in program_rlc_ram_register_setting()
[all …]
A Dgfx_v9_4.c132 SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT),
136 SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT),
140 SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT),
144 SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT),
176 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
696 WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL, 0); in gfx_v9_4_query_utc_edc_status()
700 WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL, 0); in gfx_v9_4_query_utc_edc_status()
930 WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL, 0); in gfx_v9_4_reset_ras_error_count()
934 WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL, 0); in gfx_v9_4_reset_ras_error_count()
943 RREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL); in gfx_v9_4_reset_ras_error_count()
[all …]
A Dgfx_v9_4_2.c784 WREG32_SOC15(GC, 0, regGC_THROTTLE_CTRL, tmp); in gfx_v9_4_2_set_power_brake_sequence()
788 WREG32_SOC15(GC, 0, regGC_THROTTLE_CTRL1, tmp); in gfx_v9_4_2_set_power_brake_sequence()
793 WREG32_SOC15(GC, 0, regGC_CAC_IND_DATA, tmp); in gfx_v9_4_2_set_power_brake_sequence()
896 SOC15_REG_ENTRY(GC, 0, regDC_EDC_CSINVOC_CNT),
900 SOC15_REG_ENTRY(GC, 0, regDC_EDC_RESTORE_CNT),
904 SOC15_REG_ENTRY(GC, 0, regDC_EDC_CSINVOC_CNT),
908 SOC15_REG_ENTRY(GC, 0, regDC_EDC_RESTORE_CNT),
929 SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT),
1827 WREG32_SOC15_RLC_EX(reg, GC, 0, regSQ_IND_INDEX, in wave_read_ind()
1832 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); in wave_read_ind()
[all …]
A Dgfxhub_v2_1.c159 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); in gfxhub_v2_1_init_system_aperture_regs()
217 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); in gfxhub_v2_1_init_cache_regs()
228 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp); in gfxhub_v2_1_init_cache_regs()
230 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); in gfxhub_v2_1_init_cache_regs()
233 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp); in gfxhub_v2_1_init_cache_regs()
245 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp); in gfxhub_v2_1_init_cache_regs()
250 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp); in gfxhub_v2_1_init_cache_regs()
254 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp); in gfxhub_v2_1_init_cache_regs()
405 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0); in gfxhub_v2_1_gart_disable()
468 SOC15_REG_OFFSET(GC, 0, in gfxhub_v2_1_init()
[all …]
A Dgfxhub_v1_0.c96 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BASE, 0); in gfxhub_v1_0_init_system_aperture_regs()
113 WREG32_SOC15_RLC(GC, 0, in gfxhub_v1_0_init_system_aperture_regs()
119 GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, in gfxhub_v1_0_init_system_aperture_regs()
145 WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0); in gfxhub_v1_0_init_system_aperture_regs()
177 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL); in gfxhub_v1_0_init_cache_regs()
186 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp); in gfxhub_v1_0_init_cache_regs()
188 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2); in gfxhub_v1_0_init_cache_regs()
191 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp); in gfxhub_v1_0_init_cache_regs()
365 WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0); in gfxhub_v1_0_gart_disable()
417 SOC15_REG_OFFSET(GC, 0, in gfxhub_v1_0_init()
[all …]
A Dgfxhub_v3_0.c155 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); in gfxhub_v3_0_init_system_aperture_regs()
216 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL); in gfxhub_v3_0_init_cache_regs()
227 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp); in gfxhub_v3_0_init_cache_regs()
232 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL2, tmp); in gfxhub_v3_0_init_cache_regs()
401 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, 0); in gfxhub_v3_0_gart_disable()
416 tmp = RREG32_SOC15(GC, 0, regCP_DEBUG); in gfxhub_v3_0_set_fault_enable_default()
418 WREG32_SOC15(GC, 0, regCP_DEBUG, tmp); in gfxhub_v3_0_set_fault_enable_default()
442 tmp = RREG32_SOC15(GC, 0, regSQG_CONFIG); in gfxhub_v3_0_set_fault_enable_default()
446 WREG32_SOC15(GC, 0, regSQG_CONFIG, tmp); in gfxhub_v3_0_set_fault_enable_default()
491 SOC15_REG_OFFSET(GC, 0, in gfxhub_v3_0_init()
[all …]
A Dgfx_v9_0.c719 {SOC15_REG_ENTRY(GC, 0, mmSQ_IND_INDEX)},
1758 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, in wave_read_ind()
1770 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, in wave_read_regs()
2355 tmp = RREG32_SOC15(GC, 0, mmSQ_CONFIG); in gfx_v9_0_init_sq_config()
2358 WREG32_SOC15(GC, 0, mmSQ_CONFIG, tmp); in gfx_v9_0_init_sq_config()
3015 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); in gfx_v9_0_cp_gfx_start()
3079 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); in gfx_v9_0_cp_gfx_resume()
3089 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); in gfx_v9_0_cp_gfx_resume()
3106 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); in gfx_v9_0_cp_gfx_resume()
3143 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, in gfx_v9_0_cp_compute_enable()
[all …]
A Dgfxhub_v2_0.c157 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); in gfxhub_v2_0_init_system_aperture_regs()
214 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); in gfxhub_v2_0_init_cache_regs()
225 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp); in gfxhub_v2_0_init_cache_regs()
227 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); in gfxhub_v2_0_init_cache_regs()
230 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp); in gfxhub_v2_0_init_cache_regs()
242 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp); in gfxhub_v2_0_init_cache_regs()
247 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp); in gfxhub_v2_0_init_cache_regs()
251 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp); in gfxhub_v2_0_init_cache_regs()
382 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0); in gfxhub_v2_0_gart_disable()
439 SOC15_REG_OFFSET(GC, 0, in gfxhub_v2_0_init()
[all …]
A Dgfxhub_v3_0_3.c161 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); in gfxhub_v3_0_3_init_system_aperture_regs()
221 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL); in gfxhub_v3_0_3_init_cache_regs()
232 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp); in gfxhub_v3_0_3_init_cache_regs()
234 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2); in gfxhub_v3_0_3_init_cache_regs()
237 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL2, tmp); in gfxhub_v3_0_3_init_cache_regs()
249 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp); in gfxhub_v3_0_3_init_cache_regs()
254 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL4, tmp); in gfxhub_v3_0_3_init_cache_regs()
258 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL5, tmp); in gfxhub_v3_0_3_init_cache_regs()
394 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, 0); in gfxhub_v3_0_3_gart_disable()
457 SOC15_REG_OFFSET(GC, 0, in gfxhub_v3_0_3_init()
[all …]
A Dgfx_v11_0.c731 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, in wave_read_ind()
741 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, in wave_read_regs()
1730 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); in gfx_v11_0_rlc_stop()
3082 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, in gfx_v11_0_cp_gfx_start()
3197 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); in gfx_v11_0_cp_gfx_resume()
4018 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, in gfx_v11_0_kiq_init_register()
5267 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, in gfx_v11_0_ring_set_wptr_gfx()
6108 tmp = RREG32_SOC15_IP(GC, target);
6111 WREG32_SOC15_IP(GC, target, tmp);
6118 tmp = RREG32_SOC15_IP(GC, target);
[all …]
A Dsdma_v5_0.c68 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
79 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00),
80 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
91 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00)
137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x007fffff, 0x004c5c00),
164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x007fffff, 0x004c5c00)
391 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, in sdma_v5_0_ring_set_wptr()
394 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, in sdma_v5_0_ring_set_wptr()
723 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, in sdma_v5_0_gfx_resume()
[all …]
A Damdgpu_amdkfd_gfx_v10_3.c88 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); in program_sh_mem_settings_v10_3()
118 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, in init_interrupts_v10_3()
203 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, value); in hqd_load_v10_3()
247 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, in hqd_load_v10_3()
249 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, in hqd_load_v10_3()
251 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, in hqd_load_v10_3()
257 WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1, in hqd_load_v10_3()
267 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, data); in hqd_load_v10_3()
466 act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE); in hqd_is_occupied_v10_3()
532 temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE); in hqd_destroy_v10_3()
[all …]
A Dmes_v10_1.c465 data = RREG32_SOC15(GC, 0, mmCP_MES_CNTL); in mes_v10_1_enable()
469 WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data); in mes_v10_1_enable()
494 WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data); in mes_v10_1_enable()
506 WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data); in mes_v10_1_enable()
543 WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_LO, in mes_v10_1_load_microcode()
545 WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_HI, in mes_v10_1_load_microcode()
552 WREG32_SOC15(GC, 0, mmCP_MES_MDBASE_LO, in mes_v10_1_load_microcode()
554 WREG32_SOC15(GC, 0, mmCP_MES_MDBASE_HI, in mes_v10_1_load_microcode()
745 data = RREG32_SOC15(GC, 0, mmCP_HQD_VMID);
747 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, data);
[all …]
A Dmes_v11_0.c555 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); in mes_v11_0_enable()
578 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); in mes_v11_0_enable()
594 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); in mes_v11_0_enable()
635 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, in mes_v11_0_load_microcode()
637 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, in mes_v11_0_load_microcode()
644 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, in mes_v11_0_load_microcode()
646 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, in mes_v11_0_load_microcode()
808 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); in mes_v11_0_queue_init_register()
810 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); in mes_v11_0_queue_init_register()
825 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); in mes_v11_0_queue_init_register()
[all …]
A Damdgpu_amdkfd_gfx_v10.c87 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); in kgd_program_sh_mem_settings()
148 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, in kgd_init_interrupts()
260 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, in kgd_hqd_load()
262 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, in kgd_hqd_load()
270 WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1, in kgd_hqd_load()
275 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_RPTR, in kgd_hqd_load()
280 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, data); in kgd_hqd_load()
479 act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE); in kgd_hqd_is_occupied()
608 temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE); in kgd_hqd_destroy()
683 WREG32_SOC15(GC, 0, mmSQ_CMD, sq_cmd); in kgd_wave_control_execute()
[all …]
A Damdgpu_amdkfd_gfx_v9.c169 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, in kgd_gfx_v9_init_interrupts()
282 WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1, in kgd_gfx_v9_hqd_load()
491 act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE); in kgd_gfx_v9_hqd_is_occupied()
559 temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE); in kgd_gfx_v9_hqd_destroy()
634 WREG32_SOC15(GC, 0, mmSQ_CMD, sq_cmd); in kgd_gfx_v9_wave_control_execute()
704 reg_val = RREG32_SOC15_IP(GC, SOC15_REG_OFFSET(GC, 0, mmSPI_CSQ_WF_ACTIVE_COUNT_0) + in get_wave_count()
708 *vmid = (RREG32_SOC15(GC, 0, mmCP_HQD_VMID) & in get_wave_count()
841 WREG32_SOC15(GC, 0, mmSQ_SHADER_TBA_LO, in kgd_gfx_v9_program_trap_handler_settings()
843 WREG32_SOC15(GC, 0, mmSQ_SHADER_TBA_HI, in kgd_gfx_v9_program_trap_handler_settings()
849 WREG32_SOC15(GC, 0, mmSQ_SHADER_TMA_LO, in kgd_gfx_v9_program_trap_handler_settings()
[all …]
A Damdgpu_amdkfd_gfx_v11.c114 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, in init_interrupts_v11()
193 hqd_base = SOC15_REG_OFFSET(GC, 0, regCP_MQD_BASE_ADDR); in hqd_load_v11()
232 WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_LO), in hqd_load_v11()
234 WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_HI), in hqd_load_v11()
242 WREG32(SOC15_REG_OFFSET(GC, 0, regCP_PQ_WPTR_POLL_CNTL1), in hqd_load_v11()
247 WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_EOP_RPTR), in hqd_load_v11()
252 WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_ACTIVE), data); in hqd_load_v11()
330 for (reg = SOC15_REG_OFFSET(GC, 0, regCP_MQD_BASE_ADDR); in hqd_dump_v11()
455 act = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_ACTIVE)); in hqd_is_occupied_v11()
581 WREG32(SOC15_REG_OFFSET(GC, 0, regSQ_CMD), sq_cmd); in wave_control_execute_v11()
[all …]
A Dsdma_v6_0.c213 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, in sdma_v6_0_ring_set_wptr()
216 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, in sdma_v6_0_ring_set_wptr()
724 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE)); in sdma_v6_0_soft_reset()
726 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp); in sdma_v6_0_soft_reset()
727 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); in sdma_v6_0_soft_reset()
730 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), tmp); in sdma_v6_0_soft_reset()
737 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); in sdma_v6_0_soft_reset()
738 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); in sdma_v6_0_soft_reset()
742 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, 0); in sdma_v6_0_soft_reset()
743 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); in sdma_v6_0_soft_reset()
[all …]
A Dsoc15.c298 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); in soc15_gc_cac_rreg()
309 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); in soc15_gc_cac_wreg()
320 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); in soc15_se_cac_rreg()
331 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v)); in soc15_se_cac_wreg()
379 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
380 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
387 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
393 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
396 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
398 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
[all …]
A Dsoc21.c235 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)},
236 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)},
237 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)},
238 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)},
239 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)},
240 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)},
243 { SOC15_REG_ENTRY(GC, 0, regCP_STAT)},
244 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)},
249 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)},
252 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)},
[all …]
A Dsdma_v5_2.c430 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), in sdma_v5_2_ctx_switch_enable()
432 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), in sdma_v5_2_ctx_switch_enable()
434 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), in sdma_v5_2_ctx_switch_enable()
513 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); in sdma_v5_2_gfx_resume()
515 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); in sdma_v5_2_gfx_resume()
524 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, in sdma_v5_2_gfx_resume()
710 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); in sdma_v5_2_soft_reset()
713 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); in sdma_v5_2_soft_reset()
714 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); in sdma_v5_2_soft_reset()
719 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); in sdma_v5_2_soft_reset()
[all …]
A Dnv.c387 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
388 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
389 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
390 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
391 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
392 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
395 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
396 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
401 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
404 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
[all …]
A Dgfxhub_v1_1.c53 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL_ALDE); in gfxhub_v1_1_get_xgmi_info()
55 RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE_ALDE), in gfxhub_v1_1_get_xgmi_info()
60 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL); in gfxhub_v1_1_get_xgmi_info()
62 RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE), in gfxhub_v1_1_get_xgmi_info()

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