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Searched refs:GCC_PCIE_0_PHY_BCR (Results 1 – 25 of 40) sorted by relevance

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/linux-6.3-rc2/include/dt-bindings/reset/
A Dqcom,gcc-apq8084.h91 #define GCC_PCIE_0_PHY_BCR 82 macro
/linux-6.3-rc2/include/dt-bindings/clock/
A Dqcom,gcc-sm6350.h166 #define GCC_PCIE_0_PHY_BCR 7 macro
A Dqcom,qdu1000-gcc.h149 #define GCC_PCIE_0_PHY_BCR 6 macro
A Dqcom,gcc-qcs404.h166 #define GCC_PCIE_0_PHY_BCR 10 macro
A Dqcom,gcc-sc7280.h210 #define GCC_PCIE_0_PHY_BCR 1 macro
A Dqcom,sm8550-gcc.h190 #define GCC_PCIE_0_PHY_BCR 6 macro
A Dqcom,gcc-sm8450.h206 #define GCC_PCIE_0_PHY_BCR 7 macro
A Dqcom,gcc-sdm845.h229 #define GCC_PCIE_0_PHY_BCR 24 macro
A Dqcom,gcc-sm8150.h218 #define GCC_PCIE_0_PHY_BCR 5 macro
A Dqcom,gcc-sm8250.h219 #define GCC_PCIE_0_PHY_BCR 7 macro
A Dqcom,gcc-sm8350.h221 #define GCC_PCIE_0_PHY_BCR 7 macro
A Dqcom,gcc-msm8998.h274 #define GCC_PCIE_0_PHY_BCR 76 macro
A Dqcom,sa8775p-gcc.h272 #define GCC_PCIE_0_PHY_BCR 10 macro
A Dqcom,gcc-sc8180x.h255 #define GCC_PCIE_0_PHY_BCR 5 macro
A Dqcom,gcc-msm8996.h320 #define GCC_PCIE_0_PHY_BCR 80 macro
A Dqcom,gcc-sc8280xp.h406 #define GCC_PCIE_0_PHY_BCR 4 macro
/linux-6.3-rc2/Documentation/devicetree/bindings/phy/
A Dqcom,msm8996-qmp-pcie-phy.yaml154 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
/linux-6.3-rc2/drivers/clk/qcom/
A Dgcc-qdu1000.c2546 [GCC_PCIE_0_PHY_BCR] = { 0x7c000 },
A Dgcc-qcs404.c2777 [GCC_PCIE_0_PHY_BCR] = { 0x3e004 },
A Dgcc-sm8550.c3243 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
A Dgcc-msm8998.c3169 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
A Dgcc-sm8450.c3138 [GCC_PCIE_0_PHY_BCR] = { 0x7c01c },
A Dgcc-apq8084.c3589 [GCC_PCIE_0_PHY_BCR] = { 0x1b00 },
A Dgcc-sc7280.c3387 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
A Dgcc-sm8250.c3542 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },

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