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Searched refs:GC_HWIP (Results 1 – 25 of 40) sorted by relevance

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/linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/
A Dsoc15_common.h116 __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_RLC, GC_HWIP)
123 …uint32_t r0 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG0_BASE_IDX] + prefix##SCRATCH_REG0; \
124 …uint32_t r1 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG1; \
125 …uint32_t spare_int = adev->reg_offset[GC_HWIP][0][prefix##RLC_SPARE_INT_BASE_IDX] + prefix##RLC_SP…
144 …5_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value, AMDGPU_REGS_RLC, GC_HWIP)
148 __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_RLC, GC_HWIP)
160 …uint32_t r2 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG2; \
161 …uint32_t r3 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG3; \
162 …uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][0][prefix##GRBM_GFX_CNTL_BASE_IDX] + prefix##GRBM_G…
163 …uint32_t grbm_idx = adev->reg_offset[GC_HWIP][0][prefix##GRBM_GFX_INDEX_BASE_IDX] + prefix##GRBM_G…
[all …]
A Dgmc_v9_0.c621 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2))) in gmc_v9_0_process_interrupt()
738 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) in gmc_v9_0_use_invalidate_semaphore()
789 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0)) { in gmc_v9_0_flush_gpu_tlb()
857 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2))) in gmc_v9_0_flush_gpu_tlb()
1144 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v9_0_get_coherence_flags()
1158 if (adev->ip_versions[GC_HWIP][0] == in gmc_v9_0_get_coherence_flags()
1562 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v9_0_mc_init()
1680 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v9_0_sw_init()
1712 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) in gmc_v9_0_sw_init()
1732 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) { in gmc_v9_0_sw_init()
[all …]
A Dgmc_v10_0.c153 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0))) in gmc_v10_0_process_interrupt()
253 GC_HWIP : MMHUB_HWIP; in gmc_v10_0_flush_vm_hub()
288 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0))) in gmc_v10_0_flush_vm_hub()
737 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v10_0_set_gfxhub_funcs()
855 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v10_0_mc_init()
922 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v10_0_sw_init()
940 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v10_0_sw_init()
1240 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 3) || in gmc_v10_0_get_clockgating_state()
1241 adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 4)) in gmc_v10_0_get_clockgating_state()
A Damdgpu_discovery.c173 [GC_HWIP] = GC_HWID,
1494 switch (adev->ip_versions[GC_HWIP][0]) { in amdgpu_discovery_set_common_ip_blocks()
1530 adev->ip_versions[GC_HWIP][0]); in amdgpu_discovery_set_common_ip_blocks()
1539 switch (adev->ip_versions[GC_HWIP][0]) { in amdgpu_discovery_set_gmc_ip_blocks()
1575 adev->ip_versions[GC_HWIP][0]); in amdgpu_discovery_set_gmc_ip_blocks()
1790 switch (adev->ip_versions[GC_HWIP][0]) { in amdgpu_discovery_set_gc_ip_blocks()
1826 adev->ip_versions[GC_HWIP][0]); in amdgpu_discovery_set_gc_ip_blocks()
1960 switch (adev->ip_versions[GC_HWIP][0]) { in amdgpu_discovery_set_mes_ip_blocks()
2017 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); in amdgpu_discovery_set_ip_blocks()
2172 switch (adev->ip_versions[GC_HWIP][0]) { in amdgpu_discovery_set_ip_blocks()
[all …]
A Dgfx_v9_0.c896 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_init_golden_registers()
1103 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_check_fw_write_wait()
1216 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_check_if_need_gfxoff()
1670 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_rlc_init()
1853 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_gpu_early_init()
2018 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_sw_init()
2353 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_init_sq_config()
2915 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_rlc_resume()
3975 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_get_gpu_clock_counter()
4926 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_set_powergating_state()
[all …]
A Ddimgrey_cavefish_reg_init.c35 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
A Daldebaran_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in aldebaran_reg_base_init()
A Dmes_v10_1.c304 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; in mes_v10_1_set_hw_resources()
561 switch (adev->ip_versions[GC_HWIP][0]) { in mes_v10_1_load_microcode()
571 switch (adev->ip_versions[GC_HWIP][0]) { in mes_v10_1_load_microcode()
581 switch (adev->ip_versions[GC_HWIP][0]) { in mes_v10_1_load_microcode()
590 switch (adev->ip_versions[GC_HWIP][0]) { in mes_v10_1_load_microcode()
998 switch (adev->ip_versions[GC_HWIP][0]) { in mes_v10_1_kiq_setting()
A Damdgpu_display.c746 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) in convert_tiling_flags_to_modifier()
748 else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) in convert_tiling_flags_to_modifier()
750 else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 0, 0)) in convert_tiling_flags_to_modifier()
759 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) { in convert_tiling_flags_to_modifier()
765 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) { in convert_tiling_flags_to_modifier()
821 adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0); in convert_tiling_flags_to_modifier()
858 if ((adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) && in convert_tiling_flags_to_modifier()
A Darct_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in arct_reg_base_init()
A Dgfx_v10_0.c3644 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_init_spm_golden_registers()
3667 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_init_golden_registers()
3908 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_check_fw_write_wait()
3959 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_check_gfxoff_flag()
4161 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_init_rlcg_reg_access_ctrl()
4379 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_gpu_early_init()
4510 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_sw_init()
6041 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_cp_gfx_set_doorbell()
6296 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_kiq_setting()
7002 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_check_grbm_cam_remapping()
[all …]
A Dvega10_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega10_reg_base_init()
A Dimu_v11_0.c50 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); in imu_v11_0_init_microcode()
355 switch (adev->ip_versions[GC_HWIP][0]) { in imu_v11_0_program_rlc_ram()
A Dvega20_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega20_reg_base_init()
A Dgmc_v11_0.c204 GC_HWIP : MMHUB_HWIP; in gmc_v11_0_flush_vm_hub()
621 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v11_0_set_gfxhub_funcs()
770 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v11_0_sw_init()
A Damdgpu_ucode.c1211 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) in amdgpu_ucode_legacy_naming()
1223 } else if (block_type == GC_HWIP) { in amdgpu_ucode_legacy_naming()
1224 switch (adev->ip_versions[GC_HWIP][0]) { in amdgpu_ucode_legacy_naming()
1286 case GC_HWIP: in amdgpu_ucode_ip_version_decode()
A Dmes_v11_0.c207 (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) && in mes_v11_0_add_hw_queue()
208 (adev->ip_versions[GC_HWIP][0] <= IP_VERSION(11, 0, 3)))) in mes_v11_0_add_hw_queue()
382 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; in mes_v11_0_set_hw_resources()
1288 (adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3))) in mes_v11_0_late_init()
A Damdgpu_gmc.c529 switch (adev->ip_versions[GC_HWIP][0]) { in amdgpu_gmc_tmz_set()
592 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; in amdgpu_gmc_noretry_set()
A Dsoc21.c463 switch (adev->ip_versions[GC_HWIP][0]) { in soc21_need_full_reset()
603 switch (adev->ip_versions[GC_HWIP][0]) { in soc21_common_early_init()
A Dsoc15.c483 tmp = (entry->hwip == GC_HWIP) ? in soc15_program_register_sequence()
496 (entry->hwip == GC_HWIP) ? in soc15_program_register_sequence()
957 switch (adev->ip_versions[GC_HWIP][0]) { in soc15_common_early_init()
A Damdgpu_mes.c1378 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0) && in amdgpu_mes_self_test()
1379 adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0) && in amdgpu_mes_self_test()
1437 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); in amdgpu_mes_init_microcode()
A Dsdma_v5_2.c74 base = adev->reg_offset[GC_HWIP][0][1]; in sdma_v5_2_get_reg_offset()
79 base = adev->reg_offset[GC_HWIP][0][0]; in sdma_v5_2_get_reg_offset()
83 base = adev->reg_offset[GC_HWIP][0][2]; in sdma_v5_2_get_reg_offset()
A Dgfx_v11_0.c268 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v11_0_init_golden_registers()
477 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); in gfx_v11_0_init_microcode()
816 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v11_0_gpu_early_init()
1260 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v11_0_sw_init()
2520 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 1) || in gfx_v11_0_wait_for_rlc_autoload_complete()
2521 adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 4)) in gfx_v11_0_wait_for_rlc_autoload_complete()
4756 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 3)) { in gfx_v11_0_late_init()
5096 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v11_cntl_power_gating()
5125 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v11_0_set_powergating_state()
5151 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v11_0_set_clockgating_state()
A Damdgpu_amdkfd.c712 if (IP_VERSION_MAJ(adev->ip_versions[GC_HWIP][0]) == 11) { in amdgpu_amdkfd_set_compute_idle()
/linux-6.3-rc2/drivers/gpu/drm/amd/amdkfd/
A Dkfd_device.c277 switch (adev->ip_versions[GC_HWIP][0]) { in kgd2kfd_probe()
407 if (adev->ip_versions[GC_HWIP][0]) in kgd2kfd_probe()
409 adev->ip_versions[GC_HWIP][0], vf ? "VF" : ""); in kgd2kfd_probe()

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