Searched refs:GPCR (Results 1 – 9 of 9) sorted by relevance
125 GPCR = SDA; in adv7171_start()141 GPCR = SCK; in adv7171_send()146 GPCR = SDA; in adv7171_send()151 GPCR = SCK; in adv7171_send()161 GPCR = SCK | SDA; in adv7171_send()175 GPCR = SDA | SCK | MOD; /* clear L3 mode to ensure UDA1341 doesn't respond */ in adv7171_write()190 GPCR = (~gplr) & (SDA | SCK | MOD); in adv7171_write()530 GPCR = GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM; in assabet_init()538 GPCR = GPIO_GPIO27; in assabet_init()
107 GPCR = ~gpio; in sa11x0_pm_enter()
421 GPCR = GPIO_MBGNT; in sa1110_mb_disable()440 GPCR = GPIO_MBGNT; in sa1110_mb_enable()
112 GPCR = GPIO_GPIO25; in jornada_ssp_start()
269 GPCR = GPIO_GPIO20; /* stop gpio20 */ in jornada720_init()
285 GPCR = 0x0fffffff; /* All outputs are set low by default */ in h3xxx_map_io()
35 #define GPCR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x24) macro371 GPCR(i * 32) = ~PGSR(i); in pxa2xx_mfp_suspend()395 GPCR(i * 32) = ~saved_gplr[i]; in pxa2xx_mfp_resume()
23 #define GPCR 0x04c /* pin clear w/o */ macro116 gpcr = gpio_reg(chip, offset, GPCR); in mrfld_gpio_set()
1108 #define GPCR __REG(0x9004000C) /* GPIO Pin output Clear Reg. */ macro
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